ZHCSAT8G september 2012 – october 2020 SN65DSI85
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- Parameter Measurement Information
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
5 Pin Configuration and Functions
To minimize the power supply noise floor, provide good decoupling near the SN65DSI85 power pins. The use of four ceramic capacitors (2x 0.1 μF and 2x 0.01 μF) provides good performance. At the least, it is recommended to install one 0.1 μF and one 0.01 μF capacitor near the SN65DSI85. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and device power inputs pins must be minimized. Placing the capacitor underneath the SN65DSI85 on the bottom of the PCB is often a good choice.
Figure 5-1 ZXH
Package64-Pin nFBGA(Top View)Table 5-1 Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ADDR | A1 | CMOS Input/Output | Local I2C Interface Target Address Select. See Table 7-6. In normal operation this pin is an input. When the ADDR pin is programmed high, it should be tied to the same 1.8 V power rails where the SN65DSI85 VCC 1.8 V power rail is connected. |
| A_Y0N | C9 | LVDS Output | FlatLink? Channel A LVDS Data Output 0. |
| A_Y0P | C8 | ||
| A_Y1N | D9 | FlatLink? Channel A LVDS Data Output 1. | |
| A_Y1P | D8 | ||
| A_Y2N | E9 | FlatLink? Channel A LVDS Data Output 2. | |
| A_Y2P | E8 | ||
| A_Y3N | G9 | FlatLink? Channel A LVDS Data Output 3. A_Y3P and A_Y3N shall be left NC for 18 bpp panels. | |
| A_Y3P | G8 | ||
| A_CLKN | F9 | FlatLink? Channel A LVDS Clock | |
| A_CLKP | F8 | ||
| B_Y0N | A3 | FlatLink? Channel B LVDS Data Output 0. | |
| B_Y0P | B3 | ||
| B_Y1N | A4 | FlatLink? Channel B LVDS Data Output 1. | |
| B_Y1P | B4 | ||
| B_Y2N | A5 | FlatLink? Channel B LVDS Data Output 2. | |
| B_Y2P | B5 | ||
| B_Y3N | A7 | FlatLink? Channel B LVDS Data Output 3. B_Y3P and B_Y3N shall be left NC for 18 bpp panels. | |
| B_Y3P | B7 | ||
| B_CLKN | A6 | FlatLink? Channel B LVDS Clock. | |
| B_CLKP | B6 | ||
| DA0N | J3 | LVDS Input (HS) CMOS Input (LS) (Failsafe) |
MIPI? D-PHY Channel A Data Lane 0; data rate up to 1 Gbps. |
| DA0P | H3 | ||
| DA1N | J4 | MIPI? D-PHY Channel A Data Lane 1; data rate up to 1 Gbps. | |
| DA1P | H4 | ||
| DA2N | J6 | MIPI? D-PHY Channel A Data Lane 2; data rate up to 1 Gbps. | |
| DA2P | H6 | ||
| DA3N | J7 | MIPI? D-PHY Channel A Data Lane 3; data rate up to 1 Gbps. | |
| DA3P | H7 | ||
| DACN | J5 | MIPI? D-PHY Channel A Clock Lane; operates up to 500 MHz. | |
| DACP | H5 | ||
| DB0N | C1 | MIPI? D-PHY Channel B Data Lane 0; data rate up to 1 Gbps. | |
| DB0P | C2 | ||
| DB1N | D1 | MIPI? D-PHY Channel B Data Lane 1; data rate up to 1 Gbps. | |
| DB1P | D2 | ||
| DB2N | F1 | MIPI? D-PHY Channel B Data Lane 2; data rate up to 1 Gbps. | |
| DB2P | F2 | ||
| DB3N | G1 | MIPI? D-PHY Channel B Data Lane 3; data rate up to 1 Gbps. | |
| DB3P | G2 | ||
| DBCN | E1 | MIPI? D-PHY Channel B Clock Lane; operates up to 500 MHz. | |
| DBCP | E2 | ||
| EN | B1 | CMOS Input with pullup (Failsafe) | Chip Enable and Reset. Device is reset (shutdown) when EN is low. |
| GND | A2, A8, B9, D5, E4, F4, F5, H9 | Power Supply | Reference Ground. |
| IRQ | J9 | CMOS Output | Interrupt Signal. |
| RSVD1 | H8 | CMOS Input/Output with pulldown | Reserved. This pin should be left unconnected for normal operation. |
| RSVD2 | B2 | CMOS Input with pulldown | Reserved. This pin should be left unconnected for normal operation. |
| REFCLK | H2 | CMOS Input (Failsafe) | Optional External Reference Clock for LVDS Pixel Clock. If an External Reference Clock is not used, this pin should be pulled to GND with an external resistor. The source of the reference clock should be placed as close as possible with a series resistor near the source to reduce EMI. |
| SCL | H1 | Local I2C Interface Clock. | |
| SDA | J1 | Open Drain Input/Output (Failsafe) | Local I2C Interface Bi-directional Data Signal. |
| VCC | A9, B8, D6, E5, E6, F6, J2 | Power Supply | 1.8 V Power Supply. |
| VCORE | J8 | 1.1 V Output from Voltage Regulator. This pin must have a 1 μF external capacitor to GND. | |