ZHCSAT8G september 2012 – october 2020 SN65DSI85
PRODUCTION DATA
The SN65DSI85 supports a pattern generation feature on LVDS Channels. This feature can be used to test the LVDS output path and LVDS panels in a system platform. The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C. No DSI data is received while the pattern generation feature is enabled.
There are three modes available for LVDS test pattern generation. The mode of test pattern generation is determined by register configuration as shown in the tables below.
| Test Pattern Generation Mode | Register Configurations |
|---|---|
| Single LVDS configuration mode | LVDS_LINK_CFG(CSR 0x18.4) = 1b DSI_CH_MODE(CSR 0x10.6:5) = XXb CHA_TEST_PATTERN(CSR 0x3C.4) = 1b CHB_TEST_PATTERN(CSR 0x3C.0) = 0b |
| Dual LVDS configuration mode | LVDS_LINK_CFG(CSR 0x18.4) = 0b DSI_CH_MODE(CSR 0x10.6:5) = 0Xb CHA_TEST_PATTERN(CSR 0x3C.4) = 1b CHB_TEST_PATTERN(CSR 0x3C.0) = 0b |
| Two independent LVDS configuration mode | LVDS_LINK_CFG(CSR 0x18.4) = 0b DSI_CH_MODE(CSR 0x10.6:5) = 10b CHA_TEST_PATTERN(CSR 0x3C.4) = 1b CHB_TEST_PATTERN(CSR 0x3C.0) = 1b |
The following tables show lists of video registers that need to be configured for test pattern generation video parameters.
| Bit Address | Register Name |
|---|---|
| 0x20.7:0 | CHA_ACTIVE_LINE_LENGTH_LOW |
| 0x21.3:0 | CHA_ACTIVE_LINE_LENGTH_HIGH |
| 0x24.7:0 | CHA_VERTICAL_DISPLAY_SIZE_LOW |
| 0x25.3:0 | CHA_VERTICAL_DISPLAY_SIZE_HIGH |
| 0x2C.7:0 | CHA_HSYNC_PULSE_WIDTH_LOW |
| 0x2D.1:0 | CHA_HSYNC_PULSE_WIDTH_HIGH |
| 0x30.7:0 | CHA_VSYNC_PULSE_WIDTH_LOW |
| 0x31.1:0 | CHA_VSYNC_PULSE_WIDTH_HIGH |
| 0x34.7:0 | CHA_HORIZONTAL_BACK_PORCH |
| 0x36.7:0 | CHA_VERTICAL_BACK_PORCH |
| 0x38.7:0 | CHA_HORIZONTAL_FRONT_PORCH |
| 0x3A.7:0 | CHA_VERTICAL_FRONT_PORCH |
Both Channel A and Channel B register parameters need to be configured.
| Bit Address | Register Name |
|---|---|
| Channel A | |
| 0x20.7:0 | CHA_ACTIVE_LINE_LENGTH_LOW |
| 0x21.3:0 | CHA_ACTIVE_LINE_LENGTH_HIGH |
| 0x24.7:0 | CHA_VERTICAL_DISPLAY_SIZE_LOW |
| 0x25.3:0 | CHA_VERTICAL_DISPLAY_SIZE_HIGH |
| 0x2C.7:0 | CHA_HSYNC_PULSE_WIDTH_LOW |
| 0x2D.1:0 | CHA_HSYNC_PULSE_WIDTH_HIGH |
| 0x30.7:0 | CHA_VSYNC_PULSE_WIDTH_LOW |
| 0x31.1:0 | CHA_VSYNC_PULSE_WIDTH_HIGH |
| 0x34.7:0 | CHA_HORIZONTAL_BACK_PORCH |
| 0x36.7:0 | CHA_VERTICAL_BACK_PORCH |
| 0x38.7:0 | CHA_HORIZONTAL_FRONT_PORCH |
| 0x3A.7:0 | CHA_VERTICAL_FRONT_PORCH |
| Channel B | |
| 0x22.7:0 | CHB_ACTIVE_LINE_LENGTH_LOW |
| 0x23.3:0 | CHB_ACTIVE_LINE_LENGTH_HIGH |
| 0x26.7:0 | CHB_VERTICAL_DISPLAY_SIZE_LOW |
| 0x27.3:0 | CHB_VERTICAL_DISPLAY_SIZE_HIGH |
| 0x2E.7:0 | CHB_HSYNC_PULSE_WIDTH_LOW |
| 0x2F.1:0 | CHB_HSYNC_PULSE_WIDTH_HIGH |
| 0x32.7:0 | CHB_VSYNC_PULSE_WIDTH_LOW |
| 0x33.1:0 | CHB_VSYNC_PULSE_WIDTH_HIGH |
| 0x35.7:0 | CHB_HORIZONTAL_BACK_PORCH |
| 0x37.7:0 | CHB_VERTICAL_BACK_PORCH |
| 0x39.7:0 | CHB_HORIZONTAL_FRONT_PORCH |
| 0x3B.7:0 | CHB_VERTICAL_FRONT_PORCH |