ZHCSAT8G september 2012 – october 2020 SN65DSI85
PRODUCTION DATA
| MODE | CSR 0x18.4 | CSR 0x10.7 | CSR 0x10.6:5 | DESCRIPTION |
|---|---|---|---|---|
| LVDS_LINK_CFG | LEFT_RIGHT_PIXES | DSI_CH_MODE | ||
| Single DSI Input to Single-Link LVDS | 1 | N/A | 01 | Single DSI Input on Channel A to Single-Link LVDS output on Channel A. |
| Single DSI Input to Dual-Link LVDS | 0 | N/A | 01 | Single DSI Input on Channel A to Dual-Link LVDS output with Odd pixels on Channel A and Even pixels on Channel B. |
| Dual DSI Input (Odd/Even) to Single-Link LVDS (1) | 1 | 0 | 00 | Dual DSI Input with Odd pixels received on Channel A and Even pixels received on Channel B. Data is output to Single-Link LVDS on Channel A. |
| Dual DSI Input (Odd/Even) to Dual-Link LVDS (1) | 0 | 0 | 00 | Dual DSI Input with Odd pixels received on Channel A and Even pixels received on Channel B. Data is output to Dual-Link LVDS with Odd pixels on Channel A and Even pixels on Channel B. |
| Dual DSI Input (Left/Right) to Single-Link LVDS (2) | 1 | 1 | 00 | Dual DSI Input with Left pixels received on Channel A and Right pixels received on Channel B. Data is output to Single-Link LVDS on Channel A. |
| Dual DSI Input (Left/Right) to Dual-Link LVDS (2) | 0 | 1 | 00 | Dual DSI Input with Left pixels received on Channel A and Right pixels received on Channel B. Data is output to Dual-Link LVDS with Odd pixels on Channel A and Even pixels on Channel B. |
| Dual DSI Inputs (two streams) to two Single-Link LVDS (3) | 0 | N/A | 10 | One video stream input on DSI Channel A and output to Single-Link LVDS on Channel A. Another video stream input on DSI Channel B and output to Single-Link LVDS on Channel B. |