ZHCSAU2G September 2012 – June 2018 SN65DSI84
PRODUCTION DATA.
| PIN | DESCRIPTION | ||
|---|---|---|---|
| NAME | NO. | I/O | |
| DA0P | H3 | LVDS Input (HS)
CMOS Input (LS) (Failsafe) |
MIPI® D-PHY Channel A Data Lane 0; data rate up to 1 Gbps. |
| DA0N | J3 | ||
| DA1P | H4 | MIPI® D-PHY Channel A Data Lane 1; data rate up to 1 Gbps. | |
| DA1N | J4 | ||
| DA2P | H6 | MIPI® D-PHY Channel A Data Lane 2; data rate up to 1 Gbps. | |
| DA2N | J6 | ||
| DA3P | H7 | MIPI® D-PHY Channel A Data Lane 3; data rate up to 1 Gbps. | |
| DA3N | J7 | ||
| DACP | H5 | MIPI® D-PHY Channel A Clock Lane; operates up to 500 MHz. | |
| DACN | J5 | ||
| NC | C2, C1, D2, D1, F2, F1, G2, G1, E2, E1 | No connects. | These pins should not be connected to any signal, power or ground. |
| A_Y0P | C8 | LVDS Output | FlatLink™ Channel A LVDS Data Output 0. |
| A_Y0N | C9 | ||
| A_Y1P | D8 | FlatLink™ Channel A LVDS Data Output 1. | |
| A_Y1N | D9 | ||
| A_Y2P | E8 | FlatLink™ Channel A LVDS Data Output 2. | |
| A_Y2N | E9 | ||
| A_Y3P | G8 | FlatLink™ Channel A LVDS Data Output 3. A_Y3P and A_Y3N shall be left NC for 18 bpp panels. | |
| A_Y3N | G9 | ||
| A_CLKP | F8 | FlatLink™ Channel A LVDS Clock | |
| A_CLKN | F9 | ||
| B_Y0P | B3 | FlatLink™ Channel B LVDS Data Output 0. | |
| B_Y0N | A3 | ||
| B_Y1P | B4 | FlatLink™ Channel B LVDS Data Output 1. | |
| B_Y1N | A4 | ||
| B_Y2P | B5 | FlatLink™ Channel B LVDS Data Output 2. | |
| B_Y2N | A5 | ||
| B_Y3P | B7 | FlatLink™ Channel B LVDS Data Output 3. B_Y3P and B_Y3N shall be left NC for 18 bpp panels. | |
| B_Y3N | A7 | ||
| B_CLKP | B6 | FlatLink™ Channel B LVDS Clock. | |
| B_CLKN | A6 | ||
| RSVD1 | H8 | CMOS Input/Output with pulldown | Reserved. This pin should be left unconnected for normal operation. |
| RSVD2 | B2 | CMOS Input with pulldown | Reserved. This pin should be left unconnected for normal operation. |
| ADDR | A1 | CMOS Input/Output | Local I2C Interface Target Address Select. See Table 4. In normal operation this pin is an input. When the ADDR pin is programmed high, it should be tied to the same 1.8 V power rails where the SN65DSI84 VCC 1.8 V power rail is connected. |
| EN | B1 | CMOS Input with pullup (Failsafe) | Chip Enable and Reset. Device is reset (shutdown) when EN is low. |
| REFCLK | H2 | CMOS Input (Failsafe) | Optional External Reference Clock for LVDS Pixel Clock. If an External Reference Clock is not used, this pin should be pulled to GND with an external resistor. The source of the reference clock should be placed as close as possible with a series resistor near the source to reduce EMI. |
| SCL | H1 | Local I2C Interface Clock. | |
| SDA | J1 | Open Drain Input/Output (Failsafe) | Local I2C Interface Bi-directional Data Signal. |
| IRQ | J9 | CMOS Output | Interrupt Signal. |
| GND | A2, A8, B9, D5, E4, F4, F5, H9 | Power Supply | Reference Ground. |
| VCC | A9, B8, D6, E5, E6, F6, J2 | 1.8 V Power Supply. | |
| VCORE | J8 | 1.1 V Output from Voltage Regulator. This pin must have a 1 µF external capacitor to GND. | |