ZHCSAU2G September 2012 – June 2018 SN65DSI84
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.4.1 Reset Implementation
When EN is de-asserted (low), the SN65DSI84 is in SHUTDOWN or RESET state. In this state, CMOS inputs are ignored, the MIPI® D-PHY inputs are disabled and outputs are high impedance. It is critical to transition the EN input from a low to a high level after the VCC supply has reached the minimum operating voltage as shown in Figure 6. This is achieved by a control signal to the EN input, or by an external capacitor connected between EN and GND.
Figure 6. Cold Start VCC Ramp up to EN
When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the VCC supply, where a slower ramp-up results in a larger value external capacitor. See the latest reference schematic for the SN65DSI84 device and, or consider approximately 200 nF capacitor as a reasonable first estimate for the size of the external capacitor.
Both EN implementations are shown in Figure 7 and Figure 8.
When the SN65DSI84 is reset while VCC is high, the EN pin must be held low for at least 10 ms before being asserted high as described in Table 2 to be sure that the device is properly reset. The DSI CLK lane MUST be in HS and the DSI data lanes MUST be driven to LP11 while the device is in reset before the EN pin is asserted per the timing described in Table 2.