ZHCSAU2G September   2012  – June 2018 SN65DSI84

PRODUCTION DATA.  

1. 1 特性
2. 2 應(yīng)用
3. 3 說明
   1.     典型應(yīng)用
4. 4 修訂歷史記錄
5. 5 Pin Configuration and Functions
   1.     Pin Functions
6. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 EDS Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
   6. 6.6 Switching Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
   4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
      7. 7.4.7 Operating Modes
   5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
   6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
8. 8 Application and Implementation
   1. 8.1 Application Information
      1. 8.1.1 Video Stop and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
         1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
9. 9 Power Supply Recommendations
   1. 9.1 VCC Power Supply
   2. 9.2 VCORE Power Supply
10. 10Layout
    1. 10.1 Layout Guidelines
       1. 10.1.1 Package Specific
       2. 10.1.2 Differential Pairs
       3. 10.1.3 Ground
    2. 10.2 Layout Example
11. 11器件和文檔支持
    1. 11.1 接收文檔更新通知
    2. 11.2 社區(qū)資源
    3. 11.3 商標(biāo)
    4. 11.4 靜電放電警告
    5. 11.5 術(shù)語表
12. 12機械、封裝和可訂購信息