ZHCSFS0A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Programming
- 8.5
Register Maps
- 8.5.1
Control and Status Registers Overview
- 8.5.1.1 CSR Bit Field Definitions – ID Registers
- 8.5.1.2 CSR Bit Field Definitions – Reset and Clock Registers
- 8.5.1.3 CSR Bit Field Definitions – DSI Registers
- 8.5.1.4 CSR Bit Field Definitions – LVDS Registers
- 8.5.1.5
CSR Bit Field Definitions – Video Registers
- 8.5.1.5.1 Register 0x20
- 8.5.1.5.2 Register 0x21
- 8.5.1.5.3 Register 0x24
- 8.5.1.5.4 Register 0x25
- 8.5.1.5.5 Register 0x28
- 8.5.1.5.6 Register 0x29
- 8.5.1.5.7 Register 0x2C
- 8.5.1.5.8 Register 0x2D
- 8.5.1.5.9 Register 0x30
- 8.5.1.5.10 Register 0x31
- 8.5.1.5.11 Register 0x34
- 8.5.1.5.12 Register 0x36
- 8.5.1.5.13 Register 0x38
- 8.5.1.5.14 Register 0x3A
- 8.5.1.5.15 Register 0x3C
- 8.5.1.6 CSR Bit Field Definitions – IRQ Registers
- 8.5.1
Control and Status Registers Overview
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.3.4 Reset Implementation
When the EN pin is deasserted (low), the SN65DSI83-Q1 device is in SHUTDOWN or RESET state. In this state, CMOS inputs are ignored, the MIPI D-PHY inputs are disabled and outputs are high impedance. Transitioning the EN input from a low to a high level after the VCC supply has reached the minimum operating voltage as shown in Figure 6 is critical. This transition is achieved by a control signal to the EN input, or by an external capacitor connected between EN and GND.
Figure 6. Cold-Start VCC Ramp Up to EN When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the VCC supply, where a slower ramp-up results in a larger value external capacitor. Consider an approximately 200-nF capacitor as a reasonable first estimate for the size of the external capacitor.
Figure 7 and Figure 8 show both EN implementations.
Figure 7. External Capacitor Controlled EN 
Figure 8. EN Input from Active Controller When the SN65DSI83-Q1 is reset while VCC is high, the EN pin must be held low for at least 10 ms before being asserted high as described in Table 2 to be sure that the device is properly reset. The DSI CLK lane MUST be in HS and the DSI data lanes MUST be driven to LP11 while the device is in reset before the EN pin is asserted per the timing described in Table 2.