ZHCSFS0A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
|---|---|---|---|---|---|---|
| DSI | ||||||
| tGS | DSI LP glitch suppression pulse width | 300 | ps | |||
| LVDS | ||||||
| tc | Output clock period | 6.49 | 40 | ns | ||
| tw | High-level output clock (CLK) pulse duration | 4/7 tc | ns | |||
| t0 | Delay time, CLK↑ to 1st serial bit position | tc = 6.49 ns;
Input clock jitter < 25 ps (REFCLK) See Figure 4 |
–0.15 | 0.15 | ns | |
| t1 | Delay time, CLK↑ to 2nd serial bit position | 1/7 tc – 0.15 | 1/7 tc + 0.15 | ns | ||
| t2 | Delay time, CLK↑ to 3rd serial bit position | 2/7 tc – 0.15 | 2/7 tc + 0.15 | ns | ||
| t3 | Delay time, CLK↑ to 4th serial bit position | 3/7 tc – 0.15 | 3/7 tc + 0.15 | ns | ||
| t4 | Delay time, CLK↑ to 5th serial bit position | 4/7 tc – 0.15 | 4/7 tc + 0.15 | ns | ||
| t5 | Delay time, CLK↑ to 6th serial bit position | 5/7 tc – 0.15 | 5/7 tc + 0.15 | ns | ||
| t6 | Delay time, CLK↑ to 7th serial bit position | 6/7 tc – 0.15 | 6/7 tc + 0.15 | ns | ||
| tr | Differential output rise time | See Figure 4 | 180 | 500 | ps | |
| tf | Differential output fall time | |||||
| EN, ULPS, RESET | ||||||
| ten | Enable time from EN or ULPS | tc(o) = 12.9 ns | 1 | ms | ||
| tdis | Disable time to standby; see | tc(o) = 12.9 ns | 0.1 | ms | ||
| treset | Reset yime | 10 | ms | |||
| REFCLK | ||||||
| FREFCLK | REFCLK freqeuncy. Supported frequencies:
25 MHz - 154 MHz |
25 | 154 | MHz | ||
| tr, tf | REFCLK rise and fall time | 100 × 10–12 | 1×10–9 | s | ||
| tpj | REFCLK peak-to-peak phase jitter | 50 | ps | |||
| Duty | REFCLK duty cycle | 40% | 50% | 60% | ||
| REFCLK or DSI CLK (DACP/N) | ||||||
| SSC_CLKIN | SSC enabled Input CLK center spread depth(2) | 0.5% | 1% | 2% | ||
| Modulation frequency | 30 | 60 | kHz | |||