ZHCSND7 September 2022 SN6507-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ENABLE AND UVLO | ||||||
| TEN_glitch | EN glitch filter | 5 | μs | |||
| POWER STAGE | ||||||
| tBBM | Break-before-make time | Measured at 0.5VCC with RL = 50 Ω, FSW = 1 MHz, RSR = 9.6 k? (or Default), Figure 7-2 | 70 | ns | ||
| SOFT-START | ||||||
| tPWRUP | Power-up time | CSS = 0 μF, from EN = High to full drive-current available at SW1 and SW2 | 300 | 400 | μs | |
| tPWRDN | Power-down time | CSS = 0 μF, from EN = Low to output MOSFETs off (no current on SW1 and SW2) | 30 | μs | ||