ZHCSND7 September 2022 SN6507-Q1
PRODUCTION DATA
The SN6507-Q1 has a CLK pin which can be used to synchronize the device with system clock and in turn with other SN6507-Q1 devices so that the system can control the exact switching frequency of the device. In SYNC mode, the CLK frequency is divided by two to drive the gates of powerFETs. Figure 9-2 shows the timing diagram for the same.
The device cannot automatically change from SYNC mode to switching frequency control using the internal oscillator or resistor-programmable switching frequency mode. If a valid external CLK signal is not present, the output will stop switching, and a power cycle will be required to change the switching mode back to using the internal oscillator or the adjustable switching frequency using RCLK.
When the device is in SYNC mode, duty cycle control and SSM are not supported, therefore it's recommended to leave DC pin floating in SYNC mode to reduce the solution size.
Note that it is recommended that the SN6507-Q1 VCC pin powers up before CLK pin. Before device power-up, the initial state of external clock should be high-impedance.