The SN6507-Q1 implements a duty cycle control feature to provide line regulation to a certain degree through a resistor on DC pin. By making the DC pin voltage a function of the input, the duty cycle will adjust with V_IN, so that V_OUT can be kept constant. Compared to fixed duty cycle transformer drivers, this dynamic duty cycle control feature reduces LDO power loss for wide V_IN variations by pseudo-regulating the output. For applications where input variation is within a certain range, this feature can eliminate the post-regulation LDO. Another benefit of duty cycle control is to reduce the transformer cost and size because of the limited input range to primary side of the transformer.

The calculation of DC pin resistor is shown in Equation 1, where both R_DC and R_CLK are in k?.

For fixed oscillator cases where R_CLK is shorted to GND, a value of R_CLK = 9.6k? should be used in the equation above to calculate R_DC.

The duty cycle control can compensate for input variation up to ±35%, where line regulation within ±5% can be achieved. To achieve this range, it is recommended that duty cycle at nominal V_IN is centered at 25% (D = 0.25). The transformer turns ratio needs take this duty cycle into calculation to ensure the expected output voltage level at all V_IN voltages, as discussed in Section 9.2.2.5.

The duty cycle control features supports up to a certain duty cycle and V_IN range. The minimum duty cycle is determined by the charge and discharge time of the gate capacitance of Power FETs, while the maximum duty cycle is limtied by the dead time (70 ns typical). For example, at 1 MHz, the adjustable duty cycle is between 10% and 43%. Exceeding above duty cycle range, the line regulation may saturate and input compensation does not work anymore. Meanwhile, if the duty cycle is lower than the minimum spec, the part may hit current limit at heavy loads. The V_IN range that duty cycle feature is applicable is from 6 V to 36 V.

To enable the duty cycle control feature, an inductor is required on the output side. The selection of the output inductor should make sure the inductor current will not go into discountinous conduction mode (DCM), meaning the inductor current ramp should not drop to zero at any time. The minimum inductance L_MIN is therefore calculated by the conditions that the part stays in continuous conduction mode (CCM) where the load DC current is smaller than half the current ramp amplitude seen on the inductor. Therefore L_MIN is a function of the load current and switching frequency as shown by below equation where I_load is in A, f_SW is in Hz, D is the duty cycle as a decimal (for 25% duty cycle, 0.25 would be used), and L_min is in H.