ZHCSFA5 July   2016 SM320C6457-HIREL

PRODUCTION DATA.  

1. 1器件概述
   1. 1.1 特性
   2. 1.2 應用
   3. 1.3 說明
   4. 1.4 說明 （續）
   5. 1.5 功能方框圖
2. 2修訂歷史記錄
3. 3Terminal Configuration and Functions
   1. 3.1 Pin Diagram
   2. 3.2 Pin Attributes
      1. 3.2.1 Pin Map
   3. 3.3 Signal Descriptions
4. 4Specifications
   1. 4.1 Absolute Maximum Ratings
   2. 4.2 ESD Ratings
   3. 4.3 Recommended Operating Conditions
   4. 4.4 Electrical Characteristics
   5. 4.5 Thermal Resistance Characteristics
   6. 4.6 Timing and Switching Characteristics
      1. 4.6.1 Timing Parameters and Information
         1. 4.6.1.1 1.8-V Signal Transition Levels
         2. 4.6.1.2 3.3-V Signal Transition Levels
         3. 4.6.1.3 3.3-V Signal Transition Rates
         4. 4.6.1.4 Timing Parameters and Board Routing Analysis
      2. 4.6.2 Power Supply Sequencing
         1. 4.6.2.1 Power-Supply Decoupling
         2. 4.6.2.2 Power-Down Operation
         3. 4.6.2.3 Power Supply to Peripheral I/O Mapping
      3. 4.6.3 Reset Timing
      4. 4.6.4 Clock and Control Signal Transition Behavior
   7. 4.7 Peripherals
      1. 4.7.1  Enhanced Direct Memory Access (EDMA3) Controller
         1. 4.7.1.1 EDMA3 Device-Specific Information
         2. 4.7.1.2 EDMA3 Channel Synchronization Events
         3. 4.7.1.3 EDMA3 Peripheral Register Description(s)
      2. 4.7.2  Interrupts
         1. 4.7.2.1 Interrupt Sources and Interrupt Controller
         2. 4.7.2.2 External Interrupts Electrical Data/Timing
      3. 4.7.3  Reset Controller
         1. 4.7.3.1 Power-on Reset (POR Pin)
         2. 4.7.3.2 Warm Reset (RESET Pin)
         3. 4.7.3.3 System Reset
         4. 4.7.3.4 CPU Reset
         5. 4.7.3.5 Reset Priority
         6. 4.7.3.6 Reset Controller Register
            1. 4.7.3.6.1 Reset Type Status Register
            2. 4.7.3.6.2 Software Reset Control Register
            3. 4.7.3.6.3 Reset Configuration Register
      4. 4.7.4  PLL1 and PLL1 Controller
         1. 4.7.4.1 PLL1 Controller Device-Specific Information
            1. 4.7.4.1.1 Internal Clocks and Maximum Operating Frequencies
            2. 4.7.4.1.2 PLL1 Controller Operating Modes
            3. 4.7.4.1.3 PLL1 Stabilization, Lock, and Reset Times
         2. 4.7.4.2 PLL1 Controller Memory Map
         3. 4.7.4.3 PLL1 Controller Registers
            1. 4.7.4.3.1  PLL1 Control Register
            2. 4.7.4.3.2  PLL Multiplier Control Register
            3. 4.7.4.3.3  PLL Post-Divider Control Register
            4. 4.7.4.3.4  PLL Controller Divider 3 Register
            5. 4.7.4.3.5  PLL Controller Divider 6 Register
            6. 4.7.4.3.6  PLL Controller Divider 7 Register
            7. 4.7.4.3.7  PLL Controller Divider 8 Register
            8. 4.7.4.3.8  PLL Controller Command Register
            9. 4.7.4.3.9  PLL Controller Status Register
            10. 4.7.4.3.10 PLL Controller Clock Align Control Register
            11. 4.7.4.3.11 PLLDIV Ratio Change Status Register
            12. 4.7.4.3.12 SYSCLK Status Register
         4. 4.7.4.4 PLL1 Controller Input and Output Electrical Data/Timing
      5. 4.7.5  PLL2
         1. 4.7.5.1 PLL2 Device-Specific Information
            1. 4.7.5.1.1 Internal Clocks and Maximum Operating Frequencies
            2. 4.7.5.1.2 PLL2 Operating Modes
         2. 4.7.5.2 PLL2 Input Clock Electrical Data/Timing
      6. 4.7.6  DDR2 Memory Controller
         1. 4.7.6.1 DDR2 Memory Controller Device-Specific Information
         2. 4.7.6.2 DDR2 Memory Controller Peripheral Register Description(s)
         3. 4.7.6.3 DDR2 Memory Controller Electrical Data/Timing
      7. 4.7.7  External Memory Interface A (EMIFA)
         1. 4.7.7.1 EMIFA Device-Specific Information
         2. 4.7.7.2 EMIFA Peripheral Register Description(s)
         3. 4.7.7.3 EMIFA Electrical Data/Timing
            1. 4.7.7.3.1 AECLKIN and AECLKOUT Timing
            2. 4.7.7.3.2 Asynchronous Memory Timing
            3. 4.7.7.3.3 Programmable Synchronous Interface Timing
      8. 4.7.8  I2C Peripheral
         1. 4.7.8.1 I2C Device-Specific Information
         2. 4.7.8.2 I2C Peripheral Register Description(s)
         3. 4.7.8.3 I2C Electrical Data/Timing
            1. 4.7.8.3.1 Inter-Integrated Circuits (I2C) Timing
      9. 4.7.9  Host-Port Interface (HPI) Peripheral
         1. 4.7.9.1 HPI Device-Specific Information
         2. 4.7.9.2 HPI Peripheral Register Description(s)
         3. 4.7.9.3 HPI Electrical Data/Timing
      10. 4.7.10 Multichannel Buffered Serial Port (McBSP)
          1. 4.7.10.1 McBSP Device-Specific Information
             1. 4.7.10.1.1 McBSP Peripheral Register Description(s)
          2. 4.7.10.2 McBSP Electrical Data/Timing
      11. 4.7.11 Ethernet MAC (EMAC)
          1. 4.7.11.1 EMAC Device-Specific Information
          2. 4.7.11.2 EMAC Peripheral Register Description(s)
          3. 4.7.11.3 EMAC Electrical Data/Timing (SGMII)
      12. 4.7.12 Management Data Input/Output (MDIO)
          1. 4.7.12.1 MDIO Peripheral Register Description(s)
          2. 4.7.12.2 MDIO Electrical Data/Timing
      13. 4.7.13 Timers
          1. 4.7.13.1 Timers Device-Specific Information
             1. 4.7.13.1.1 Timer Watchdog Select
          2. 4.7.13.2 Timers Peripheral Register Description(s)
          3. 4.7.13.3 Timers Electrical Data/Timing
      14. 4.7.14 Enhanced Viterbi-Decoder Coprocessor (VCP2)
          1. 4.7.14.1 VCP2 Device-Specific Information
          2. 4.7.14.2 VCP2 Peripheral Register Description
      15. 4.7.15 Enhanced Turbo Decoder Coprocessor (TCP2)
          1. 4.7.15.1 TCP2 Device-Specific Information
      16. 4.7.16 UTOPIA
          1. 4.7.16.1 UTOPIA Device-Specific Information
          2. 4.7.16.2 UTOPIA Peripheral Register Description(s)
          3. 4.7.16.3 UTOPIA Electrical Data/Timing
      17. 4.7.17 Serial RapidIO (SRIO) Port
          1. 4.7.17.1 Serial RapidIO Device-Specific Information
          2. 4.7.17.2 Serial RapidIO Peripheral Register Description(s)
          3. 4.7.17.3 Serial RapidIO Electrical Data/Timing
      18. 4.7.18 General-Purpose Input/Output (GPIO)
          1. 4.7.18.1 GPIO Device-Specific Information
          2. 4.7.18.2 GPIO Peripheral Register Description(s)
          3. 4.7.18.3 GPIO Electrical Data/Timing
      19. 4.7.19 Emulation Features and Capability
          1. 4.7.19.1 Advanced Event Triggering (AET)
          2. 4.7.19.2 Trace
             1. 4.7.19.2.1 Trace Electrical Data/Timing
          3. 4.7.19.3 IEEE 1149.1 JTAG
             1. 4.7.19.3.1 IEEE 1149.1 JTAG Compatibility Statement
             2. 4.7.19.3.2 JTAG Electrical Data/Timing
             3. 4.7.19.3.3 HS-RTDX Electrical Data/Timing
5. 5Detailed Description
   1. 5.1 Device Overview
   2. 5.2 CPU (DSP Core) Description
   3. 5.3 C64x+ Megamodule
      1. 5.3.1 Memory Architecture
         1. 5.3.1.1 L1P Memory
         2. 5.3.1.2 L1D Memory
         3. 5.3.1.3 L2 Memory
         4. 5.3.1.4 L3 Memory
      2. 5.3.2 Memory Protection
      3. 5.3.3 Bandwidth Management
      4. 5.3.4 Power-Down Control
      5. 5.3.5 Megamodule Resets
      6. 5.3.6 Megamodule Revision
      7. 5.3.7 C64x+ Megamodule Register Descriptions
   4. 5.4 Memory Map Summary
   5. 5.5 Device Configuration
      1. 5.5.1 Device Configuration at Device Reset
      2. 5.5.2 Peripheral Selection After Device Reset
      3. 5.5.3 Device State Control Registers
      4. 5.5.4 Device Status Register Description
      5. 5.5.5 JTAG ID (JTAGID) Register Description
      6. 5.5.6 Pullup/Pulldown Resistors
   6. 5.6 System Interconnect
      1. 5.6.1 Internal Buses, Bridges, and Switch Fabrics
      2. 5.6.2 Data Switch Fabric Connections
      3. 5.6.3 Configuration Switch Fabric
      4. 5.6.4 Bus Priorities
   7. 5.7 Boot Modes
      1. 5.7.1 Second-Level Bootloaders
      2. 5.7.2 Boot Sequence
   8. 5.8 Rake Search Accelerator (RSA)
6. 6器件和文檔支持
   1. 6.1 器件命名規則
   2. 6.2 工具與軟件
   3. 6.3 文檔支持
      1. 6.3.1 接收文檔更新通知
   4. 6.4 社區資源
   5. 6.5 商標
   6. 6.6 靜電放電警告
   7. 6.7 Glossary
7. 7機械、封裝和可訂購信息