ZHCSX36K July 2001 – September 2024 PCF8574
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.4 Device Functional Modes
Figure 7-3 and Figure 7-4 show the address and timing diagrams for the write and read modes, respectively.
Figure 7-3 Write Mode (Output)
A. A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). The transfer of data can be stopped at any moment bya stop condition. When this occurs, data present at the latest ACK phase is valid (output mode). Input data is lost.
Figure 7-4 Read Mode (Input)