ZHCSNI8J September 2006 – March 2021 PCA9534A
PRODUCTION DATA
- 1 特性
- 2 說明
- 3 Revision History
- 4 Description (Continued)
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
- 9 Detailed Description
- 10Application Information Disclaimer
- 11Power Supply Recommendations
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
9.3.2.4.2 Reads
The bus master first must send the PCA9534A address with the least-significant bit set to a logic 0 (see Figure 9-6 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data from the register defined by the command byte then is sent by the PCA9534A (see Figure 9-10 and Figure 9-11). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data.
Figure 9-10 Read From Register