ZHCSPQ7A december 2022 – april 2023 MCT8315A
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Output Stage
- 7.3.2 Device Interface
- 7.3.3 Step-Down Mixed-Mode Buck Regulator
- 7.3.4 AVDD Linear Voltage Regulator
- 7.3.5 Charge Pump
- 7.3.6 Slew Rate Control
- 7.3.7 Cross Conduction (Dead Time)
- 7.3.8 Speed Control
- 7.3.9 Starting the Motor Under Different Initial Conditions
- 7.3.10 Motor Start Sequence (MSS)
- 7.3.11 Closed Loop Operation
- 7.3.12 Speed Loop
- 7.3.13 Input Power Regulation
- 7.3.14 Anti-Voltage Surge (AVS)
- 7.3.15 Output PWM Switching Frequency
- 7.3.16 Fast Start-up (< 50 ms)
- 7.3.17 Fast Deceleration
- 7.3.18 Active Demagnetization
- 7.3.19 Motor Stop Options
- 7.3.20 FG Configuration
- 7.3.21
Protections
- 7.3.21.1 VM Supply Undervoltage Lockout
- 7.3.21.2 AVDD Undervoltage Lockout (AVDD_UV)
- 7.3.21.3 BUCK Undervoltage Lockout (BUCK_UV)
- 7.3.21.4 VCP Charge Pump Undervoltage Lockout (CPUV)
- 7.3.21.5 Overvoltage Protection (OVP)
- 7.3.21.6 Overcurrent Protection (OCP)
- 7.3.21.7 Buck Overcurrent Protection
- 7.3.21.8
Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
- 7.3.21.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
- 7.3.21.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
- 7.3.21.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
- 7.3.21.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
- 7.3.21.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
- 7.3.21.9 Lock Detection Current Limit (LOCK_ILIMIT)
- 7.3.21.10 Thermal Warning (OTW)
- 7.3.21.11 Thermal Shutdown (TSD)
- 7.3.21.12 Motor Lock (MTR_LCK)
- 7.3.21.13 Motor Lock Detection
- 7.3.21.14 SW VM Undervoltage Protection
- 7.3.21.15 SW VM Overvoltage Protection
- 7.3.21.16 IPD Faults
- 7.4 Device Functional Modes
- 7.5 External Interface
- 7.6 EEPROM access and I2C interface
- 7.7 EEPROM (Non-Volatile) Register Map
- 7.8 RAM (Volatile) Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.3.8.2 PWM Mode Speed Control
PWM based speed control can be configured by setting SPD_CTRL_MODE to 01b. In this mode, the PWM duty cycle applied to the SPEED pin can be varied from 0 to 100% and duty command (DUTY_CMD) varies linearly with the applied PWM duty cycle. When 0 ≤ DutySPEED ≤ DutyEN_SB, DUTY_CMD is set to zero and the motor is stopped. When DutyEX_SB ≤ DutySPEED ≤ 100%, DUTY_CMD varies linearly with DutySPEED as shown in Figure 7-16. DutyEX_SB and DutyEN_SB are the standby entry and exit thresholds - refer Section 7.4.1.2 for more information on DutyEX_SB and DutyEN_SB. The frequency of the PWM input signal applied to the SPEED pin is defined as fPWM and the range for this frequency can be configured through SPD_PWM_RANGE_SELECT.
- fPWM is the frequency of the PWM signal the device can accept at SPEED pin to control motor speed. It does not correspond to the PWM output frequency that is applied to the motor phases. The PWM output frequency can be configured through PWM_FREQ_OUT (see Section 7.3.15).
- SLEEP_TIME should be set longer than the off time in PWM signal (VSPEED < VIL) at lowest duty input. For example, if fPWM is 10 kHz and lowest duty input is 2%, SLEEP_TIME should be more than 98 μs to ensure there is no unintended sleep entry.
Figure 7-16 PWM Mode Speed Control