ZHCSSV1 august 2023 MCF8316C-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Output Stage
- 7.3.2 Device Interface
- 7.3.3 Step-Down Mixed-Mode Buck Regulator
- 7.3.4 AVDD Linear Voltage Regulator
- 7.3.5 Charge Pump
- 7.3.6 Slew Rate Control
- 7.3.7 Cross Conduction (Dead Time)
- 7.3.8 Motor Control Input Sources
- 7.3.9 Starting the Motor Under Different Initial Conditions
- 7.3.10 Motor Start Sequence (MSS)
- 7.3.11 Closed Loop Operation
- 7.3.12 Motor Parameters
- 7.3.13 Motor Parameter Extraction Tool (MPET)
- 7.3.14 Anti-Voltage Surge (AVS)
- 7.3.15 Active Braking
- 7.3.16 Output PWM Switching Frequency
- 7.3.17 PWM Modulation Schemes
- 7.3.18 Dead Time Compensation
- 7.3.19 Motor Stop Options
- 7.3.20 FG Configuration
- 7.3.21 DC Bus Current Limit
- 7.3.22
Protections
- 7.3.22.1 VM Supply Undervoltage Lockout
- 7.3.22.2 AVDD Undervoltage Lockout (AVDD_UV)
- 7.3.22.3 BUCK Under Voltage Lockout (BUCK_UV)
- 7.3.22.4 VCP Charge Pump Undervoltage Lockout (CPUV)
- 7.3.22.5 Overvoltage Protection (OVP)
- 7.3.22.6 Overcurrent Protection (OCP)
- 7.3.22.7 Buck Overcurrent Protection
- 7.3.22.8 Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
- 7.3.22.9 Lock Detection Current Limit (LOCK_ILIMIT)
- 7.3.22.10 FET Thermal Warning (OTW)
- 7.3.22.11 FET Thermal Shutdown (TSD_FET)
- 7.3.22.12 Motor Lock (MTR_LCK)
- 7.3.22.13 Motor Lock Detection
- 7.3.22.14 MPET Faults
- 7.3.22.15 IPD Faults
- 7.4 Device Functional Modes
- 7.5 External Interface
- 7.6 EEPROM access and I2C interface
- 7.7 EEPROM (Non-Volatile) Register Map
- 7.8 RAM (Volatile) Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
5 Pin Configuration and Functions
Figure 5-1 MCF8316C-Q1, 40-Pin VQFN With Exposed
Thermal Pad, Top View| PIN | 40-pin package | TYPE(1) | DESCRIPTION |
|---|---|---|---|
| NAME | MCF8316C-Q1 | ||
| AGND | 26 | GND | Device analog ground. Refer Layout Guidelines for connection recommendation. |
| ALARM | 39 | O | Alarm signal:
push-pull output. Pulled logic high during fault condition, if
enabled. If ALARM pin is not used, leave it floating. |
| AVDD | 27 | PWR O | 3.3-V internal regulator output. Connect a X5R or X7R, 1-μF, 6.3-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 20 mA for external circuits. |
| BRAKE | 35 | I | High → Brake the
motor Low → Normal motor operation If BRAKE pin is not used, connect to AGND directly. If BRAKE pin is used to brake the motor, use an (optional) external 10-k? pull-down resistor (to AGND) for better noise rejection. |
| CP | 8 | PWR | Charge pump output. Connect a X5R or X7R, 1-μF, 16-V ceramic capacitor between the CP and VM pins. |
| CPH | 7 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device. |
| CPL | 6 | PWR | |
| DACOUT1 | 36 | O | DAC output DACOUT1 |
| DACOUT2 | 37 | O | DAC output DACOUT2 |
| DACOUT2/SOX | 38 | O | Multi-purpose pin: DAC output when configured as DACOUT2 CSA output when configured as SOX |
| DGND | 2 | GND | Device digital ground. Refer Layout Guidelines for connection recommendation. |
| DIR | 34 | I | Direction of motor
spinning; When low, phase driving sequence is OUT A → OUT C → OUT B When high, phase driving sequence is OUT A → OUT B → OUT C If DIR pin is not used, connect to AGND or AVDD directly (depending on phase driving sequence needed). If DIR pin is used for changing motor spin direction, use an (optional) external 10-k? pull-down resistor (to AGND) for better noise rejection. |
| DRVOFF | 21 | I | Coast (Hi-Z) all six
MOSFETs as long as DRVOFF is high. If DRVOFF pin is not used, connect to AGND directly. If DRVOFF pin is to be used for instantly coasting (Hi-Z) the MOSFETs, use an external 10-k? pull-down resistor (to AGND) for better noise rejection. |
| DVDD | 1 | PWR | 1.5-V internal regulator output. Connect a X5R or X7R, 2.2-μF, 6.3-V ceramic capacitor between the DVDD and DGND pins. |
| EXT_CLK | 33 | I | External clock reference input in external clock reference mode. |
| EXT_WD | 32 | I | External watchdog input. |
| FB_BK | 3 | PWR I/O | Feedback for buck regulator output control. Connect to buck regulator output after the inductor/resistor. |
| FG | 29 | O | Motor speed indicator : open-drain output that requires an external pull-up resistor to 1.8-V to 5.0-V. An optional internal pull-up resistor to AVDD is enabled by setting PULLUP_ENABLE to 1b; no external pull-up resistor should be used when internal pull-up resistor is enabled. |
| GND_BK | 4 | GND | Buck regulator ground. Refer Layout Guidelines for connection recommendation. |
| NC | 22, 23, 24, 25 | - | No connection. Leave these pins floating. These pins can also be tied to AGND plane and thermal pad for better heat dissipation. |
| nFAULT | 40 | O | Fault indicator. Pulled logic-low with fault condition; open-drain output that requires an external pull-up resistor to 1.8-V to 5.0-V. An optional internal pull-up resistor to AVDD is enabled by setting PULLUP_ENABLE to 1b; no external pull-up resistor should be used when internal pull-up resistor is enabled. |
| OUTA | 13, 14 | PWR O | Half-bridge output A |
| OUTB | 16, 17 | PWR O | Half-bridge output B |
| OUTC | 19, 20 | PWR O | Half-bridge output C |
| PGND | 12, 15, 18 | GND | Device power ground. Refer Layout Guidelines for connection recommendation. |
| SCL | 31 | I | I2C clock input |
| SDA | 30 | I/O | I2C data line |
| SPEED/WAKE | 28 | I | Device speed input; supports analog, PWM or frequency based speed input. The speed pin input mode can be configured through SPEED_MODE. |
| SW_BK | 5 | PWR | Buck switch node. Connect this pin to an inductor or resistor. |
| VM | 9, 10, 11 | PWR I | Device and motor power supply. Connect to motor supply voltage; bypass to PGND with one 0.1-μF capacitor plus one bulk capacitor. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device. |
| Thermal pad | GND | Must be connected to AGND. |