ZHCSHY8 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Address: 0x12
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| BUCK0_SHUTDOWN_DELAY[3:0] | BUCK0_STARTUP_DELAY[3:0] |
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7:4 | BUCK0_SHUTDOWN_DELAY[3:0] | R/W | X | Shutdown delay of the BUCK0 regulator from the falling edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table.
0h = 0 ms 1h = 1 ms Fh = 15 ms |
| 3:0 | BUCK0_STARTUP_DELAY[3:0] | R/W | X | Start-up delay the of the BUCK0 regulator from the rising edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table.
0h = 0 ms 1h = 1 ms Fh = 15 ms |