ZHCSHY8 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Address: 0x06
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| EN_BUCK2 | EN_PIN_CTRL2 | BUCK2_EN_PIN_SELECT[1:0] | EN_ROOF_FLOOR2 | EN_RDIS2 | BUCK2_FPWM | BUCK2_FPWM_MP | |
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7 | EN_BUCK2 | R/W | X | This bit enables the BUCK2 regulator.
0h = BUCK2 regulator is disabled 1h = BUCK2 regulator is enabled |
| 6 | EN_PIN_CTRL2 | R/W | X | This bit enables the EN1, EN2, EN3 pin control for the BUCK2 regulator.
0h = Only the EN_BUCK2 bit controls BUCK2 1h = EN_BUCK2 bit AND ENx pin control BUCK2 |
| 5:4 | BUCK2_EN_PIN_SELECT[1:0] | R/W | X | This bit enables the EN1, EN2, EN3 pin control for the BUCK2 regulator.
0h = EN_BUCK2 bit AND EN1 pin control the BUCK2 regulator 1h = EN_BUCK2 bit AND EN2 pin control the BUCK2 regulator 2h = EN_BUCK2 bit AND EN3 pin control the BUCK2 regulator 3h = Reserved |
| 3 | EN_ROOF_FLOOR2 | R/W | 0h | This bit enables the roof and floor control of EN1, EN2, EN3 pin if the EN_PIN_CTRL2 bit is set to 1h.
0h = Enable and disable (1/0) control 1h = Roof and floor (1/0) control |
| 2 | EN_RDIS2 | R/W | 1h | Enable output discharge resistor when BUCK2 is disabled.
0h = Discharge resistor disabled 1h = Discharge resistor enabled |
| 1 | BUCK2_FPWM | R/W | X | This bit forces the BUCK2 regulator to operate in PWM mode.
0h = Automatic transitions between PFM and PWM modes (AUTO mode) 1h = Forced to PWM operation |
| 0 | BUCK2_FPWM_MP | R/W | X | This bit forces the BUCK2 regulator to operate always in multiphase and forced-PWM operation mode.
0h = Automatic phase adding and phase shedding 1h = Forced to multiphase operation; two phases in the 2-phase configuration |