SNVSD24 August 2025 LP5814I
PRODUCTION DATA
| I2C Timing Requirements | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|
| Standard-mode | |||||
| fSCL | SCL clock frequency | 0 | 100 | kHz | |
| 1 | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 4 | μs | ||
| 2 | LOW period of the SCL clock | 4.7 | μs | ||
| 3 | HIGH period of the SCL clock | 4 | μs | ||
| 4 | Set-up time for a repeated START condition | 4.7 | μs | ||
| 5 | Data hold time | 0 | μs | ||
| 6 | Data set-up time | 250 | ns | ||
| 7 | Rise time of both SDA and SCL signals | 1000 | ns | ||
| 8 | Fall time of both SDA and SCL signals | 300 | ns | ||
| 9 | Set-up time for STOP condition | 4 | μs | ||
| 10 | Bus free time between a STOP and START condition | 4.7 | μs | ||
| Cb | Capacitive load for each bus line | 400 | pF | ||
| Fast-mode | |||||
| fSCL | SCL clock frequency | 0 | 400 | kHz | |
| 1 | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 0.6 | μs | ||
| 2 | LOW period of the SCL clock | 1.3 | μs | ||
| 3 | HIGH period of the SCL clock | 0.6 | μs | ||
| 4 | Set-up time for a repeated START condition | 0.6 | μs | ||
| 5 | Data hold time | 0 | μs | ||
| 6 | Data set-up time | 100 | ns | ||
| 7 | Rise time of both SDA and SCL signals | 300 | ns | ||
| 8 | Fall time of both SDA and SCL signals | 300 | ns | ||
| 9 | Set-up time for STOP condition | 0.6 | μs | ||
| 10 | Bus free time between a STOP and START condition | 1.3 | μs | ||
| Cb | Capacitive load for each bus line | 400 | pF | ||
| Fast-mode Plus | |||||
| fSCL | SCL clock frequency | 0 | 1000 | kHz | |
| 1 | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 0.26 | μs | ||
| 2 | LOW period of the SCL clock | 0.5 | μs | ||
| 3 | HIGH period of the SCL clock | 0.26 | μs | ||
| 4 | Set-up time for a repeated START condition | 0.26 | μs | ||
| 5 | Data hold time | 0 | μs | ||
| 6 | Data set-up time | 50 | ns | ||
| 7 | Rise time of both SDA and SCL signals | 120 | ns | ||
| 8 | Fall time of both SDA and SCL signals | 120 | ns | ||
| 9 | Set-up time for STOP condition | 0.26 | μs | ||
| 10 | Bus free time between a STOP and START condition | 0.5 | μs | ||
| Cb | Capacitive load for each bus line | 550 | pF | ||