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ZHCSOM1K April 2006 – December 2024 LP2950 , LP2951

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

D|8
- MSOI002K
DRG|8
- MPDS151C

散熱焊盤機械數據 (封裝 | 引腳)

DRG|8
- QFND084H

訂購信息

5.5 Electrical Characteristics (Both Legacy and New Chip)

V_IN = V_OUT (nominal) + 1V, I_L = 100μA, C_L = 1μF (for new chip) and C_L = 2.2μF (for legacy chip),
8-pin version: FEEDBACK tied to V_TAP, OUTPUT tied to SENSE, V_SHUTDOWN ≤ 0.7V

PARAMETER	TEST CONDITIONS		T_J	MIN	TYP	MAX	UNIT
3.3-V VERSION (LP295x-33)
Output voltage	I_L = 100μA	Legacy chip	25°C	3.267	3.3	3.333	V
		Legacy chip	–40°C to 125°C	3.234	3.3	3.366
		New chip	25°C	3.2868	3.3	3.3132
		New chip	–40°C to 125°C	3.2736	3.3	3.3264
5-V VERSION (LP295x-50)
Output voltage	I_L = 100μA	Legacy chip	25°C	4.95	5	5.05	V
		Legacy chip	–40°C to 125°C	4.900	5	5.100
		New chip	25°C	4.98	5	5.02
		New chip	–40°C to 125°C	4.96	5	5.04
ALL VOLTAGE OPTIONS
Output voltage accuracy	V_IN = [V_OUT(NOM) + 1V] to 30V, I_L = 100μA to 100mA	New chip	–40°C to 125°C	–1		1	%
Output voltage accuracy	V_IN = [V_OUT(NOM) + 1V] to 30V, I_L = 100μA to 100mA , LP (TO-92) package	New chip	–40°C to 125°C	–1.2		1.2	%
Output voltage temperature coefficient⁽¹⁾	I_L = 100μA	Legacy chip	–40°C to 125°C		20	100	ppm/°C
Output voltage temperature coefficient⁽¹⁾	I_L = 100μA	New chip	–40°C to 125°C		20	60	ppm/°C
Line regulation⁽²⁾	V_IN = [V_OUT(NOM) + 1 V] to 30V	Legacy chip	25°C		0.03	0.2	%/V
		Legacy chip	–40°C to 125°C			0.4
		New chip	25°C		0.0006	0.01
		New chip	–40°C to 125°C			0.015
Load regulation⁽²⁾	I_L = 100μA to 100mA	Legacy chip	25°C		0.04	0.2	%
		Legacy chip	–40°C to 125°C			0.3
		New chip	25°C		0.04	0.1
		New chip	–40°C to 125°C			0.2
Dropout voltage	V_IN = 2V, I_L = 100μA	Legacy chip	25°C		50	80	mV
		Legacy chip	–40°C to 125°C			150
		New chip	25°C		1	4
		New chip	–40°C to 125°C			5
	V_IN = 2V, I_L = 100mA	Legacy chip	25°C		380	450
		Legacy chip	–40°C to 125°C			600
		New chip	25°C		340	420
		New chip	–40°C to 125°C			570
GND current	I_L = 100μA	Legacy chip	25°C		75	120	μA
		Legacy chip	–40°C to 125°C			140
		New chip	25°C		50	65
		New chip	–40°C to 125°C			80
	I_L = 100mA	Legacy chip	25°C		8	12	mA
		Legacy chip	–40°C to 125°C			14
		New chip	25°C			0.8
		New chip	–40°C to 125°C			0.9
Dropout ground current	V_IN = V_OUT(NOM) – 0.5V, I_L = 100μA	Legacy chip	25°C		110	170	μA
		Legacy chip	–40°C to 125°C			200
		New chip	25°C		78	120
		New chip	–40°C to 125°C			150
UVLO V_IN rising	I_L = 100μA	New chip	–40°C to 125°C	1.8	1.9	2.0	V
UVLO V_IN falling				1.7	1.8	1.9	V
Hysteresis					100		mV
Current limit	V_OUT = 0V	Legacy chip	25°C		160	200	mA
		Legacy chip	–40°C to 125°C			220
		New chip	25°C		180	200
		New chip	–40°C to 125°C			230
Thermal regulation⁽³⁾	I_L = 100μA	Legacy chip	25°C		0.05	0.2	%/W
Thermal regulation⁽³⁾	I_L = 100μA	New chip	25°C		0.05	0.2	%/W
Output noise (RMS), 10Hz to 100KHz	C_L = 1μF (5V only)	Legacy chip	25°C		430		μV
	C_L = 1μF (5V only)	New chip	25°C		265
	C_L = 200μF	Legacy chip	25°C		160
	C_L = 100μF	New chip	25°C		250
	C_L = 3.3μF, C_Bypass = 0.01μF between pins 1 and 7	Legacy chip	25°C		100
	C_L = 3.3μF, C_Bypass = 0.01μF between pins 1 and 7	New chip	25°C		100
Power supply ripple rejection	V_IN - V_OUT = 1V, frequency = 100Hz, I_OUT ≥ 5mA	New chip	25°C		80		dB
(LP2951-xx) 8-PIN VERSION ONLY ADJ
Reference voltage		Legacy chip	25°C	1.218	1.235	1.252	V
		Legacy chip	–40°C to 125°C	1.212		1.257
		New chip	25°C	1.192	1.2	1.208
		New chip	–40°C to 125°C	1.189		1.211
Reference voltage	V_IN = 2.3V to 30V, I_L = 100μA to 100mA	Legacy chip	–40°C to 125°C	1.2		1.272
Reference voltage	V_IN = 2.3V to 30V, I_L = 100μA to 100mA	New chip	–40°C to 125°C	1.188		1.212
Reference voltage temperature coefficient⁽¹⁾		Legacy chip	25°C		20		ppm/°C
Reference voltage temperature coefficient⁽¹⁾		New chip	25°C		5		ppm/°C
FEEDBACK bias current		Legacy chip	25°C		20	40	nA
		Legacy chip	–40°C to 125°C			60
		New chip	25°C		10	50
		New chip	–40°C to 125°C			60
FEEDBACK bias current temperature coefficient		Legacy chip	25°C		0.1		nA/°C
FEEDBACK bias current temperature coefficient		New chip	25°C		0.1		nA/°C
ERROR COMPARATOR
Output leakage current	V_OUT = 30V	Legacy chip	25°C		0.01	1	μA
		Legacy chip	–40°C to 125°C			2
		New chip	25°C		0.2	0.5
		New chip	–40°C to 125°C			1
Output low voltage	V_IN ≥ 2V I_OL = 400μA	Legacy chip	25°C		150	250	mV
		Legacy chip	–40°C to 125°C			400
		New chip	25°C		180	250
		New chip	–40°C to 125°C			350
Upper threshold voltage (ERROR output high)⁽⁴⁾		Legacy chip	25°C	40	60		mV
		Legacy chip	–40°C to 125°C	25
		New chip	25°C	40	60
		New chip	–40°C to 125°C	25
Lower threshold voltage (ERROR output low)⁽⁴⁾		Legacy chip	25°C		75	95	mV
		Legacy chip	–40°C to 125°C			140
		New chip	25°C		75	95
		New chip	–40°C to 125°C			140
Hysteresis⁽⁴⁾		Legacy chip	25°C		15		mV
Hysteresis⁽⁴⁾		New chip	25°C		15		mV
SHUTDOWN INPUT
Input logic voltage	Low (regulator ON)	Legacy chip	–40°C to 125°C			0.7	V
	Low (regulator ON)	New chip	–40°C to 125°C			0.7
	High (regulator OFF)	Legacy chip	–40°C to 125°C	2
	High (regulator OFF)	New chip	–40°C to 125°C	2
SHUTDOWN input current	SHUTDOWN = 2.4V	Legacy chip	25°C		30	50	μA
		Legacy chip	–40°C to 125°C			100
		New chip	25°C		0.2	0.5
		New chip	–40°C to 125°C			1
	SHUTDOWN = 30V	Legacy chip	25°C		450	600
		Legacy chip	–40°C to 125°C			750
		New chip	25°C		0.3	0.5
		New chip	–40°C to 125°C			1
Regulator output current in shutdown	V_SHUTDOWN≥ 2V, V_IN ≥ 30V, V_OUT = 0, FEEDBACK tied to V_TAP	Legacy chip	25°C		3	10	μA
		Legacy chip	–40°C to 125°C			20
		New chip	25°C		4	6
		New chip	–40°C to 125°C			7.5

(1) Output or reference voltage temperature coefficient is defined as the worst-case voltage change divided by the total temperature range.

(2) Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to heating effects are covered under the specification for thermal regulation.

(3) Thermal regulation is defined as the change in output voltage at a time (T) after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for a 50-mA load pulse at V_IN = 30V, V_OUT = 5V (1.25W pulse) for t = 10ms.

(4) Comparator thresholds are expressed in terms of a voltage differential equal to the nominal reference voltage (measured at V_IN – V_OUT = 1V) minus FEEDBACK terminal voltage. To express these thresholds in terms of output voltage change, multiply by the error amplifier gain = V_OUT/V_REF = (R1 + R2)/R2. For example, at a programmed output voltage of 5V, the ERROR output is specified to go low when the output drops by 95mV × 5V/1.2V = 395mV. Thresholds remain constant as a percentage of V_OUT (as V_OUT is varied), with the low-output warning occurring at 6% below nominal (typ) and 7.7%(max).