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ZHCSE75D September 2015 – June 2018 LMZ36002

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RVQ|43
- MPQF400A

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics

Over -40°C to +105°C free-air temperature, PV_IN = 24 V, V_OUT = 5 V, I_OUT = I_OUT_(max), ƒ_sw = 500 kHz, C_IN1 = 1 × 10-µF, 100-V 1210 ceramic, C_IN2 = 1 × 100-µF 100-V electrolytic bulk, and C_OUT = 3 × 47-µF, 16-V 1210 ceramic (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
INPUT VOLTAGE (PV_IN)
PV_IN	Input voltage range	Over I_OUT range		4.5⁽¹⁾		60	V
UVLO	PV_IN undervoltage lockout	PV_IN increasing			3.2	3.8	V
UVLO	PV_IN undervoltage lockout	PV_IN decreasing			2.8		V
OUTPUT VOLTAGE
V_OUT_(ADJ)	Output voltage adjust range	Over I_OUT range		2.5		7.5	V
V_OUT	Set-point voltage tolerance	T_A = 25°C, I_OUT = 300 mA			±0.7%	±1.5⁽²⁾
	Temperature variation	-40°C ≤ T_A ≤ 105°C, I_OUT = 0 A			±0.9%
	Line regulation	T_A = 25°C, Over PV_IN range, I_OUT = 300 mA			±0.1%
	Load regulation	T_A = 25°C, I_OUT = 300 mA to I_OUT max			±0.3%
	Total output voltage variation	Includes set-point, line, load, and temperature			±2%
V_OUT ripple	Output voltage ripple	20-MHz Bandwidth			10%		mV/pp
OUTPUT CURRENT
I_OUT	Output current	T_A = 105°C, natural convection		0		1.5	A
I_OUT	Output current	T_A = 105°C, 200LFM		0		2	A
I_OUT	Output current	T_A = 95°C, natural convection		0		2	A
I_LIM	Overcurrent threshold				2.5		A
PERFORMANCE
η	Efficiency	PV_IN = 12 V I_OUT = 1 A	V_OUT = 7.5 V, ƒ_SW = 400 kHz		95%
			V_OUT = 5 V, ƒ_SW = 200 kHz		93%
			V_OUT = 5 V, ƒ_SW = 500 kHz		92%
			V_OUT = 3.3 V, ƒ_SW= 200 kHz		90%
			V_OUT = 2.5 V, ƒ_SW = 200 kHz		87%
		PV_IN = 24 V I_OUT = 1 A	V_OUT = 7.5 V, ƒ_SW = 400 kHz		92%
			V_OUT = 5 V, ƒ_SW= 250 kHz		90%
			V_OUT = 5 V, ƒ_SW= 500 kHz		88%
			V_OUT = 3.3 V, ƒ_SW = 250 kHz		86%
			V_OUT = 2.5 V, ƒ_SW = 250 kHz		81%
	Transient response	I_OUT = 50% load step 1 A/µs slew rate	Recovery time		100		µs
	Transient response	I_OUT = 50% load step 1 A/µs slew rate	Over/Undershoot		2%
SLOW START
t_SS	Internal soft-start time	SS/TR pin open			4.1		ms
INHIBIT
V_INH (high)	Inhibit control	Precision inhibit level		2.00	2.1	2.42	V
V_INH (hys)	Inhibit control	Inhibit turn-off hysteresis			–0.294		V
I_I (shutdown)	Input shutdown supply current	INH/UVLO pin conected to AGND			2.4	6.2⁽³⁾	µA
POWER GOOD (PWRGD)
V_PWRGD	PWRGD thresholds	V_OUT rising	Good		95%
		V_OUT rising	Fault		110%
		V_OUT falling	Fault		90%
		V_OUT falling	Good		105%
THERMAL SHUTDOWN
T_SHUTDOWN	Thermal shutdown	Shutdown Temperature			160		°C
T_SHUTDOWN	Thermal shutdown	Hysteresis			10		°C
INPUT/OUTPUT CAPACITANCE
C_IN	External input capacitance	ceramic		10⁽⁴⁾			µF
C_IN	External input capacitance	non-ceramic			100		µF
C_OUT	External output capacitance	Ceramic		64⁽⁵⁾		Note⁽⁶⁾	µF
		Non-ceramic			100	Note⁽⁶⁾	µF
		ceramic + non-ceramic				Note⁽⁶⁾	µF
		Equivalent series resistance (ESR)				20	mΩ

(1) The minimum PV_IN is 4.5 V or (V_OUT / 0.75), whichever is greater. For V_OUT = 3.3 V, the minimum PV_IN is 4.75 V when I_OUT > 1.5 A.

(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance is affected by the tolerance of the external R_SET resistor.

(3) Specified by design. Not production tested.

(4) The specified minimum ceramic input capacitance represents the standard capacitance value. The actual effective capacitance after considering the effects of DC bias and temperature variation should be ≥ 4.7 µF.

(5) The amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection). The minimum required output capacitance must be comprised of ceramic capacitance. The amount of required ceramic capacitance represents the standard capacitance value. Locate the capacitance close to the device. Adding additional ceramic or non-ceramic capacitance close to the load improves the response of the regulator to load transients.

(6) The maximum allowable output capacitance varies depending on the output voltage (see Output Capacitor Selection).