ZHCSIE8C June 2018 – October 2020 LMR33630-Q1
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE | ||||||
| VIN | Minimum operating input voltage | 3.8 | V | |||
| IQ | Non-switching input current; measured at VIN pin (2) | VFB = 1.2 V | 24 | 34 | μA | |
| ISD | Shutdown quiescent current; measured at VIN pin | EN = 0 | 5 | 10 | μA | |
| ENABLE | ||||||
| VEN-VCC-H | EN input level required to turn on internal LDO | Rising threshold | 1 | V | ||
| VEN-VCC-L | EN input level required to turn off internal LDO | Falling threshold | 0.3 | V | ||
| VEN-H | EN input level required to start switching | Rising threshold | 1.2 | 1.231 | 1.26 | V |
| VEN-HYS | Hysteresis below VEN-H | Hysteresis below VEN-H; falling | 100 | mV | ||
| ILKG-EN | Enable input leakage current | VEN = 3.3 V | 0.2 | nA | ||
| INTERNAL SUPPLIES | ||||||
| VCC | Internal LDO output voltage appearing at the VCC pin | 6 V ≤ VIN ≤ 36 V | 4.75 | 5 | 5.25 | V |
| VBOOT-UVLO | Bootstrap voltage undervoltage lock-out threshold(3) | 2.2 | V | |||
| VOLTAGE REFERENCE (FB PIN) | ||||||
| VFB | Feedback voltage; ADJ option | 0.985 | 1 | 1.015 | V | |
| IFB | Current into FB pin; ADJ option | FB = 1 V | 0.2 | 50 | nA | |
| CURRENT LIMITS(4) | ||||||
| ISC | High-side current limit | LMR33630 | 3.85 | 4.5 | 5.05 | A |
| ILIMIT | Low-side current limit | LMR33630 | 2.9 | 3.5 | 4.1 | A |
| IPEAK-MIN | Minimum peak inductor current | LMR33630 | 0.69 | A | ||
| IZC | Zero current detector threshold | -0.106 | A | |||
| SOFT START | ||||||
| tSS | Internal soft-start time | 2.9 | 4 | 6 | ms | |
| POWER GOOD (PG PIN) | ||||||
| VPG-HIGH-UP | Power-good upper threshold - rising | % of FB voltage | 105% | 107% | 110% | |
| VPG-HIGH-DN | Power-good upper threshold - falling | % of FB voltage | 103% | 105% | 108% | |
| VPG-LOW-UP | Power-good lower threshold - rising | % of FB voltage | 92% | 94% | 97% | |
| VPG-LOW-DN | Power-good lower threshold - falling | % of FB voltage | 90% | 92% | 95% | |
| tPG | Power-good glitch filter delay(1) | 60 | 170 | μs | ||
| RPG | Power-good flag RDSON | VIN = 12 V, VEN = 4 V | 76 | 150 | ? | |
| VEN = 0 V | 35 | 60 | ||||
| VIN-PG | Minimum input voltage for proper PG function | 50-μA, EN = 0 V | 2 | V | ||
| VPG | PG logic low output | 50-μA, EN = 0 V, VIN = 2V | 0.2 | V | ||
| OSCILLATOR | ||||||
| ?SW | Switching frequency | "A" Version | 340 | 400 | 460 | kHz |
| ?SW | Switching frequency | "B" Version | 1.2 | 1.4 | 1.6 | MHz |
| ?SW | Switching frequency | "C" Version, RNX package | 1.8 | 2.1 | 2.3 | MHz |
| MOSFETS | ||||||
| RDS-ON-HS | High-side MOSFET ON-resistance | RNX package | 75 | 145 | mΩ | |
| RDS-ON-LS | Low-side MOSFET ON-resistance | RNX package | 50 | 95 | mΩ | |