ZHCSKE0B March 2017 – October 2019 LMH1208
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|---|
| FSCL | SMBUS SCL frequency | 10 | 400 | kHz | ||
| TBUF | Bus free time between stop and start condition | See Figure 1. | 1.3 | µs | ||
| THD:STA | Hold time after (repeated) start condition | After this period, the first clock is generated. | 0.6 | µs | ||
| TSU:STA | Repeated start condition setup time | See Figure 1. | 0.6 | µs | ||
| TSU:STO | Stop condition setup time | See Figure 1. | 0.6 | µs | ||
| THD:DAT | Data hold time | See Figure 1. | 0 | ns | ||
| TSU:DAT | Data setup time | See Figure 1. | 100 | ns | ||
| TLOW | Clock low period | See Figure 1. | 1.3 | µs | ||
| THIGH | Clock high period | See Figure 1. | 0.6 | µs | ||
| TR | Clock and data rise time | See Figure 1. | 300 | ns | ||
| TF | Clock and data fall time | See Figure 1. | 300 | ns | ||
| TPOR | SMBus ready time after POR | Time from minimum VDDIO to SMBus valid write or read access | 50 | ms | ||