The device is designed to be used with a wide variety of LC filters. TI generally recommends using as little output capacitance as possible to keep cost and size down. Choose the output capacitor or capacitors, C_OUT, with care as it directly affects the steady-state output-voltage ripple, loop stability, and the voltage over/undershoot during load current transients.

The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the equivalent series resistance (ESR) of the output capacitors:

The other is caused by the inductor current ripple charging and discharging the output capacitors:

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of the two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens, output capacitors provide the required charge before the inductor current can slew to the appropriate level. The initial output voltage step is equal to the load current step multiplied by the ESR. V_OUT continues to droop until the control loop response increases or decreases the inductor current to supply the load. To maintain a small overshoot or undershoot during a transient, small ESR, and large capacitance are desired. But these also come with higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output voltage deviation.

For a given input and output requirement, Equation 20 gives an approximation for an absolute minimum output cap required:

Equation 20.

Along with this for the same requirement, calculate the maximum ESR as per Equation 21:

Equation 21.

where

• r = ripple ratio of the inductor ripple current (Δi_L / I_OUT)
• ΔV_O = target output voltage undershoot
• D’ = 1 – duty cycle
• f_SW = switching frequency
• I_OUT = load current

A general guideline for C_OUT range is that C_OUT must be larger than the minimum required output capacitance calculated by Equation 20. Limit the maximum value of total output capacitance to between 800 μF and 1200 μF. Large values of output capacitance can prevent the regulator from starting up correctly and adversely effect the loop stability. If values greater than the given range are to be used, then a careful study of start-up at full load and loop stability must be performed.

In applications with V_OUT less than 3.3 V, it is critical that low ESR output capacitors are selected. This limits potential output voltage overshoots as the input voltage falls below the device normal operating range. To optimize the transient behavior a feedforward capacitor can be added in parallel with the upper feedback resistor. For this design example, three 47-μF, 10-V, X7R ceramic capacitors are used in parallel.