ZHCSLG2B September 2021 – August 2022 LM74722-Q1
PRODUCTION DATA
The PD pin provides a 50-μA drive and 88-mA peak pulldown strength for the load disconnect switch stage. Connect the Gate of the FET to PD pin. Place a 18-V Zener (Dz) across the FET gate and source.
For inrush current limiting, connect CdVdT capacitor and R1 as shown in Figure 8-2.
The CdVdT capacitor is required for slowing down the PD voltage ramp during power up for inrush current limiting. Use Equation 1 to calculate CdVdT capacitance value.
where IPD_DRV is 50 μA (typical), IINRUSH is the inrush current, and COUT is the output load capacitance. An extra resistor, R1, in series with the CdVdT capacitor improves the turn-off time.
PD is pulled low during the following conditions:
During an OV event with the OV pin voltage rising above the V(OVR) threshold
When the EN pin is pulled low with V(EN) driven lower than V(EN_IL) level
When the voltage at VS pin drops below the V(VS POR) falling threshold
During these conditions, the FET Q1 turns OFF with its GATE connected to its SOURCE terminal through the external Zener (Dz).
Use Equation 2 to the peak power dissipated in the LM74722-Q1 at the instance of PD pulldown.
where
In the system designs with input voltage above 48 V, TI recommends to place a resistor, RPD, in series with the PD pin as shown in Figure 8-2. The peak power dissipation during the pulldown events gets distributed in RPD and the internal PD switch. A resistor value in the range of 270 ? to 330 ? can be selected to limit the device power dissipation within the safe limits.