7.3.1 Synchronous Step-Down Regulator

The LM73605/6 is a synchronous buck converter with both power MOSFETs integrated in the device. Figure 10 shows a simplified schematic for synchronous and non-synchronous buck converters. The synchronous buck integrates both high-side (HS) and low-side (LS) power MOSFETs. The non-synchronous buck integrates HS MOSFET and works with a discrete power diode as LS rectifier.

Figure 10. Simplified Synchronous vs Non-synchronous Buck Converters

A synchronous converter with integrated HS and LS MOSFETs offers benefits such as less design effort, lower external components count, reduced total solution size, higher efficiency at heavier load, easier PCB design, and more control flexibility.

The main advantage of a synchronous converter is that the voltage drop across the LS MOSFET is lower than the voltage drop across the power diode of a non-synchronous converter. Lower voltage drop translates into less power dissipation and higher efficiency. The LM73605/6 integrates HS and LS MOSFETs with very low on-time resistance to improve efficiency. It is especially beneficial when the output voltage is low. Because the LS MOSFET is integrated into the device, at light loads a synchronous converter has the flexibility to operate in either discontinuous or continuous conduction mode.

An integrated LS MOSFET also allows the controller to obtain inductor current information when the LS switch is on. It allows the control loop to make more complex decisions based on HS and LS currents. It allows the LM73605/6 to have peak and valley cycle-by-cycle current limiting for more robust protection.

7.3.2 Auto Mode and FPWM Mode

The LM73605/6 has configurable auto mode or FPWM options.

In auto mode, the device operates in diode emulation mode (DEM) at light loads. In DEM, inductor current stops flowing when it reaches 0 A. This is also referred to as discontinuous conduction mode (DCM). This is the same behavior as the non-synchronous regulator, with higher efficiency. At heavier load, when the inductor current valley is above 0 A, the device operates in continuous conduction mode (CCM), where the switching frequency is fixed and set by RT pin.

In auto mode, the peak inductor current has a minimum limit, I_{PEAK_MIN}, in the LM73605/6. When peak current reaches I_{PEAK_MIN}, the switching frequency reduces to regulate the required load current. Switching frequency lowers when load reduces. This is when the device operates in pulse frequency modulation (PFM). PFM further improves efficiency by reducing switching losses. Light load efficiency is especially important for battery operated systems.

In forced PWM (FPWM) mode, the device operates in CCM regardless of load with the frequency set by RT pin or synchronization input. Inductor current can go negative at light loads. At light loads, the efficiency is lower than auto mode, due to higher conduction losses and switching losses. In FPWM, the device has fixed switching frequency over the entire load range, which is beneficial to noise sensitive applications.

Figure 11 shows the inductor current waveforms in each mode with heavy load, light load, and very light load. The difference between the two modes is at lighter loads where inductor current valley reaches zero.

Figure 11. Inductor Current Waveforms at Auto Mode and FPWM Mode with Different Loads

In CCM, the inductor current peak-to-peak ripple can be estimated by Equation 1:

Equation 1.

The average or DC value of the inductor current equals the load current, or output current I_OUT, in steady state. Peak inductor current can be calculated by Equation 2

Valley inductor current can be calculated by Equation 3

In auto mode, the CCM to DCM boundary condition is when I_VALLEY = 0 A. When I_Lripple ≥ I_{PEAK_MIN}, the load current at the DCM boundary condition can be found by Equation 4. When the peak-to-peak ripple current is smaller than I_Lripple ≥ I_PEAK-MIN, the PFM boundary will be reached first.

In auto mode, the PFM operation boundary condition is when I_PEAK = I_{PEAK_MIN}. Frequency foldback occurs when peak current drops to I_{PEAK_MIN}, no matter whether in CCM or DCM operation. When current ripple is small, I_Lripple < I_{PEAK_MIN}, the peak current reaches I_{PEAK_MIN} when still in CCM. The output current at CCM PFM boundary can be found by Equation 5

The current ripple increases with reduced frequency if load reduces. When valley current reaches zero, the frequency continues to fold back with constant peak current and discontinuous current.

In FPWM mode, there is no I_PEAK-MIN limit. The peak current is defined by Equation 2 at light loads and heavy loads.

See Frequency Synchronization and Mode Setting for mode setting options in LM73605/6. Mode setting only affects operation at light loads. There is no difference if load current is above the DCM and PFM boundary conditions discussed above.

7.3.3 Fixed-Frequency Peak Current-Mode Control

The LM73605/6 synchronous switched mode voltage regulator employs fixed frequency peak current mode control with advanced features. The fixed switching frequency is controlled by an internal clock. To get accurate DC load regulation, a voltage feedback loop is implemented to generate peak current command. The HS switch is turned on at the rising edge of the clock. As shown in Figure 12, during the HS switch on-time t_ON, the SW pin voltage V_SW swings up to approximately V_IN, and the inductor current I_L increases with a linear slope. The HS switch is turned off when the inductor current reaches the peak current command. During the HS switch off-time t_OFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the V_SW to swing below ground by the voltage drop across the LS switch. The LS switch is turned off at the next clock cycle, before the HS switch is turned on. The regulation loop adjusts the peak current command to maintain a constant output voltage.

Figure 12. SW Voltage and Inductor Current Waveforms in CCM

Duty cycle D is defined by the on-time of the HS switch over the switching period:

In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inverse proportional to the input voltage: D = V_OUT ⁄ V_IN.

When the LM73605/6 is set to operate in auto mode, the LS switch is turned off when its current reaches zero ampere before the next clock cycle comes. Both HS switch and LS switch are off before the HS switch is turned on at the next clock cycle.

7.3.4 Adjustable Output Voltage

The voltage regulation loop in the LM73605/6 regulates the FB pin voltage to be the same as the internal reference voltage. The output voltage of the LM73605/6 is set by a resistor divider to program the ratio from V_OUT to V_FB. The resistor divider is connected from the output to ground with the mid-point connecting to the FB pin.

Figure 13. Output Voltage Setting by Resistor Divider

The internal voltage reference and feedback loop produce precise voltage regulation over temperature. TI recommends using divider resistors with 1% tolerance or better, and with temperature coefficient of 100 ppm or lower. Typically, R_FBT = 10 kΩ to 100 kΩ is recommended. Larger R_FBT and R_FBB values reduce the quiescent current going through the divider, which help maintain high efficiency at very light load. But larger divider values also make the feedback path more susceptible to noise. If efficiency at very light load is critical in a certain application, R_FBT up to 1 MΩ can be used.

R_FBB can be calculated by Equation 7:

Equation 7.

The minimum programmable V_OUT equals V_FB, with R_FBB open. The maximum V_OUT is limited by the maximum duty cycle at a given frequency:

Ideally, without frequency foldback, V_{OUT_MAX} = V_{IN_MIN} × D_MAX.

Power losses in the circuit reduces the maximum output voltage. The LM73605/6 folds back switching frequency under t_{OFF_MIN} condition to further extend V_{OUT_MAX}. The device maintains output regulation with lower input voltage. The minimum fold-back frequency is limited by the maximum HS on-time, t_{ON_MAX}. Maximum output voltage with frequency foldback can be estimated by:

Equation 9.

The voltage drops on the HS MOSFET and inductor DCR have been taken into account in Equation 9. The switching losses were not included.

If the resistor divider is not connected properly, the output voltage cannot be regulated because the feedback loop cannot obtain correct output voltage information. If the FB pin is shorted to ground or disconnected, the output voltage is driven close to V_IN. The load connected to the output could be damaged under this condition. Do not short FB to ground or leave it open circuit during operation.

The FB pin is a noise sensitive node. It is important to place the resistor divider as close as possible to the FB pin, and route the feedback node with a short and thin trace. The trace connecting V_OUT to R_FBT can be long, but it must be routed away from the noisy area of the PCB. For more layout recommendations, see Layout.

7.3.5 Enable and UVLO

The LM73605/6 regulates output voltage when the VCC voltage is higher than the undervoltage lock out (UVLO) level, V_{CC_UVLO}, and the EN voltage is higher than V_{EN_VOUT_H}.

The internal LDO output voltage VCC is turned on when the EN voltage is higher than V_{EN_VCC_H}. The precision enable circuitry is also turned on when VCC is above UVLO. Normal operation of the LM73605/6 with regulated output voltage is enabled when the EN voltage is greater than V_{EN_VOUT_H}. When the EN voltage is less than V_{EN_VCC_L}, the device is in shutdown mode. The internal dividers make sure V_{EN_VOUT_H} is always higher than V_{EN_VCC_H}.

The EN pin cannot be left floating. The simplest way to enable the operation of the LM73605/6 is to connect the EN pin to PVIN, which allows self-start-up of the LM73605/6 when V_IN rises. Use of a pullup resistor between PVIN and EN pins helps reduce noise coupling from PVIN pin to the EN pin.

Many applications benefit from employing an enable divider to establish a customized system UVLO. This can be used either for sequencing, system timing requirement, or to reduce the occurrence of deep discharge of a battery power source. Figure 14 shows how to use a resistor divider to set a system UVLO level. An external logic output can also be used to drive the EN pin for system sequencing.

Figure 14. System UVLO

With a selected R_ENT, the R_ENB can be calculated by:

Equation 10.

where

• V_{IN_ON_H} is the desired supply voltage threshold to turn on this device

Note that the divider adds to supply quiescent current by V_IN / (R_ENT + R_ENB). Small R_ENT and R_ENB values add more quiescent current loss. However, large divider values make the node more sensitive to noise. R_ENT in the hundreds of kΩ range is a good starting point.

7.3.6 Internal LDO, V_{CC_UVLO}, and BIAS Input

The LM73605/6 integrates an internal LDO, generating VCC voltage for control circuitry and MOSFET drivers. The VCC pin must have a 1-µF to 4.7-µF bypass capacitor placed as close as possible to the pin and properly grounded. Do not load the VCC pin or short it to ground during operation. Shorting VCC pin to ground during operation may damage the device.

The UVLO on VCC voltage, V_{CC_UVLO}, turns off the regulation when VCC voltage is too low. It prevents the LM73605/6 from operating until the VCC voltage is enough for the internal circuitry. Hysteresis on V_{CC_UVLO} prevents the part from turning off during power up if V_IN droops due to input current demands. The LDO generates VCC voltage from one of the two inputs: the supply voltage V_IN, or the BIAS input. When BIAS is tied to ground, the LDO input is V_IN. When BIAS is tied to a voltage higher than 3.3 V, the LDO input is V_BIAS. BIAS voltage must be lower than both V_IN and 18 V.

The BIAS input is designed to reduce the LDO power loss. The LDO power loss is:

The higher the difference between the input and output voltages of the LDO, the more loss occurs to supply the same LDO output current. The BIAS input provides an option to supply the LDO with a lower voltage than V_IN, to reduce the difference of the input and output voltages of the LDO and reduce power loss. For example, if the LDO current is 10 mA at a certain frequency with V_IN = 24 V and V_OUT = 5 V. The LDO loss with BIAS tied to ground is equal to 10 mA × (24 V – 3.27 V) = 207.3 mW, while the loss with BIAS tied to V_OUT is equal to 10 mA × (5 – 3.27) = 17.3 mW.

The efficiency improvement is more significant at light and mid loads because the LDO loss is a higher percentage in the total loss. The improvements is more significant with higher switching frequency because the LDO current is higher at higher switching frequency. The improvement is more significant when V_IN » V_OUT because the voltage difference is higher.

Figure 15 and Figure 16 show efficiency improvement with bias tied to V_OUT in a V_OUT = 5 V and f_SW = 2200 kHz application, in auto mode and FPWM mode, respectively.

VOUT = 5 V

fSW = 2200 kHz

Auto Mode

Figure 15. LM73606 Efficiency Comparison With Bias = V_OUT to Bias = GND in Auto Mode

VOUT = 5 V

fSW = 2200 kHz

FPWM Mode

Figure 16. LM73606 Efficiency Comparison With Bias = V_OUT to Bias = GND in FPWM Mode

TI recommends tying the BIAS pin to V_OUT when V_OUT is equal to or greater than 3.3 V and no greater than 18 V. Tie the BIAS pin to ground when not in use. A ceramic capacitor, C_BIAS, can be used from the BIAS pin to ground for bypassing. If V_OUT has high frequency noise or spikes during transients or fault conditions, a resistor (1 to 10 Ω) connected between V_OUT to BIAS can be used together with C_BIAS for filtering.

The VCC voltage is typically 3.27 V. When the LM73605/6 is operating in PFM mode with frequency foldback, VCC voltage is reduced to 3.1 V (typical) to further decrease the quiescent current and improve efficiency at very light loads. Figure 17 shows an example of VCC voltage change with mode change.

VOUT = 5 V

fSW = 500 kHz

VIN = 12 V

Figure 17. VCC Voltage vs Load Current

VCC voltage has an internal undervoltage lockout threshold, V_{CC_UVLO}. When VCC voltage is higher than V_{CC_UVLO} rising threshold, the device is active and in normal operation if V_EN > V_{EN_VOUT_H}. If VCC voltage droops below V_{CC_UVLO} falling threshold, the V_OUT is shut down.

7.3.7 Soft Start and Voltage Tracking

The LM73605/6 features controlled output voltage ramp during start-up. The soft-start feature reduces inrush current during start-up and improves system performance and reliability.

If the SS/TRK pin is floating, the LM73605/6 starts up following the fixed internal soft-start ramp.

If longer soft-start time is desired, an external capacitor can be added from SS/TRK pin to ground. There is a 2-µA (typical) internal current source, I_SSC, to charge the external capacitor. For a desired soft-start time t_SS, capacitance of C_SS can be found by Equation 12.

The FB voltage always follows the lower potential of the internal voltage ramp or the voltage on the SS/TRK pin. Thus, the soft-start time can only be extended longer than the internal soft-start time by connecting C_SS. Use C_SS to extend soft-start time when there are a large amount of output capacitors, or the output voltage is high, or the output is heavily loaded during start-up.

LM73605/6 is operating in diode emulation mode during start-up regardless of mode setting. The device is capable of starting up into pre-biased output conditions. During start-up, the device sets the minimum inductor current to zero to avoid back charging the input capacitors.

LM73605/6 can track an external voltage ramp applied to the SS/TRK pin, if the ramp is slower than the internal soft-start ramp. The external ramp final voltage after start-up must be greater than 1.5 V to avoid noise interfering with the reference voltage. Figure 18 shows how to use resistor divider to set V_OUT to follow an external ramp.

Figure 18. Soft Start Tracking External Ramp

V_OUT tracking also provides the option of ramping up faster than the internal start-up ramp. The FB voltage always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin. Figure 19 shows the case when V_OUT ramps slower than the internal ramp, while Figure 20 shows when V_OUT ramps faster than the internal ramp. If the tracking ramp is delayed after the internal ramp is completed, V_FB follows the tracking ramp even if it is faster than the internal ramp. Faster start-up time may result in large inductor current during start-up. Use with special care.

Figure 19. Tracking With Longer Start-up Time than the Internal Ramp

Figure 20. Tracking With Shorter Start-up Time than the Internal Ramp

The SS/TRK pin is discharged to ground by an internal pulldown resistor R_SSD when the output voltage is shutting down, such as in the event of UVLO, thermal shutdown, hiccup, or V_EN = 0. If a large C_SS is used, and the time when V_EN = 0 V is very short, the C_SS may not be fully discharged before the next soft start. Under this condition, the FB voltage follows the internal ramp slew rate until the voltage on C_SS is reached, then follow the slew rate defined by C_SS.

7.3.8 Adjustable Switching Frequency

The internal oscillator frequency is controlled by the impedance on the RT pin. If the RT pin is open circuit, the LM73605/6 operates at its default switching frequency, 500 kHz. The RT pin is not designed to be connected directly to ground. To program the switching frequency by R_T resistor, Equation 13, or Figure 21, or Table 1 can be used to find the resistance value.

Equation 13.

Figure 21. R_T Resistance vs Switching Frequency

The choice of switching frequency is usually a compromise between conversion efficiency and the size of the solution. Lower switching frequency has lower switching losses (including gate charge losses, switch transition losses, etc.). It usually results in higher overall efficiency. However, higher switching frequency allows the use of smaller power inductor and output capacitors, hence a more compact design. Lower inductance also helps transient response (higher large signal slew rate of inductor current), and has lower DCR. The optimal switching frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis. Factors that need to be taken into account include input voltage range, output voltage, most frequent load current level(s), external component choices, solution size/cost requirements, efficiency and thermal management requirements.

The choice of switching frequency may also be limited whether an operating condition triggers t_{ON_MIN} or t_OFF-MIN. Minimum on-time, t_ON-MIN, is the smallest time that the HS switch can be on. Minimum OFF-time, t_OFF-MIN, is the smallest duration that the HS switch can be off.

In CCM operation, t_ON-MIN and t_{OFF_MIN} limits the voltage conversion range given a selected switching frequency, F_SW. The minimum duty cycle allowed is:

The maximum duty cycle allowed is:

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution size and efficiency. The maximum operational supply voltage can be found by:

At lower supply voltage, the switching frequency decreases once t_OFF-MIN is tripped. The minimum V_IN without frequency foldback can be approximated by:

With a desired V_OUT, the range of allowed V_IN is narrower with higher switching frequency.

LM73605/6 has an advanced frequency fold-back algorithm under both t_{ON_MIN} and t_{OFF_MIN} conditions. With frequency foldback, stable output voltage regulation is extended to wider range of supply voltages.

At very high V_IN conditions, where t_{ON_MIN} limitation is met, the switching frequency reduces to allow higher V_IN while maintaining V_OUT regulation. Note that the peak to peak inductor current ripple will increase with higher V_IN and lower frequency. TI does not recommend designing the circuit to operate with t_{ON_MIN} under typical conditions.

At very low V_IN conditions, where t_{OFF_MIN} limitation is met, the switching frequency decreases until t_{ON_MAX} condition is met. Such frequency fold-back mechanism allows the LM73605/6 to have very low dropout voltage regardless of frequency setting.

7.3.9 Frequency Synchronization and Mode Setting

The LM73605/6 switching action can synchronize to an external clock from 350 kHz to 2.2 MHz. TI recommends connecting the external clock to the SYNC/MODE pin with an appropriate termination resistor. Ground the SYNC/MODE pin if not used.

Figure 22. Frequency Synchronization

Recommendations for the external clock include a high level no lower than 2 V, low level no higher than 0.4 V, duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the external clock fails at logic high or low, the LM73605/6 switches at the frequency programmed by the R_T resistor after a time-out period. TI recommends connecting a resistor to the RT pin such that the internal oscillator frequency is the same as the external clock frequency. This allows the regulator to continue operating at approximately the same switching frequency if the external clock fails with the same control loop behavior.

The SYNC/MODE pin is also used as an operation mode control input.

• To set the operation in auto mode, connect SYNC/MODE pin to ground, or a logic signal lower than 0.3 V.
• To set the operation in FPWM mode, connect SYNC/MODE pin to a bias voltage or logic signal greater than 0.6 V.
• When the LM73605/6 is synchronized to an external clock, the operation mode is FPWM.

7.3.10 Internal Compensation and C_FF

The LM73605/6 is internally compensated. The internal compensation is designed such that the loop response is stable over a wide operating frequency and output voltage range. The internal R-C values are 500 kΩ and 30 pF respectively.

When large resistance value (MΩ) is used for R_FBT, the pole formed by an internal parasitic capacitor and R_FBT can be low enough to reduce the phase margin. If only low ESR output capacitors (ceramic types) are used for C_OUT, the control loop could have low phase margin. To provide a phase boost an external feed-forward capacitor (C_FF) can be added in parallel with R_FBT. Choose the C_FF capacitor to provide most phase boost at the estimated crossover frequency f_X:

Equation 18.

where

• K = 20.27 with LM73605
• K = 24.16 with LM73606

Select C_OUT so that the f_X is no higher than 1/6 of the switching frequency. Typically, f_X / f_SW = 1/10 to 1/8 provides a good combination of stability and performance.

Place the external feed-forward capacitor in parallel with the top resistor divider R_FBT when additional phase boost is needed.

Figure 23. Feed-Forward Capacitor for Loop Compensation

The feed-forward capacitor C_FF in parallel with R_FBT places an additional zero before the crossover frequency of the control loop to boost phase margin. The zero frequency can be found by Equation 19:

An additional pole is also introduced with C_FF at the frequency of:

Select the C_FF so that the bandwidth of the control loop without the C_FF is centered between f_Z-CFF and f_P-CFF. The zero at f_Z-CFF adds phase boost at the crossover frequency and improves transient response. The pole at f_P-CFF helps maintaining proper gain margin at frequency beyond the crossover.

The need of C_FF depends on R_FBT and C_OUT. Typically, choose R_FBT ≤ 100 kΩ. C_FF may not be required, because the internal parasitic pole is at higher frequency. If C_OUT has larger ESR, and ESR zero f_Z-ESR = 1 / (2π × ESR × C_OUT) is low enough to provide phase boost around the crossover frequency, do not use C_FF. Equation 21 was tested for ceramic output capacitors:

Equation 21.

The C_FF creates a time constant with R_FBT that couples in the attenuated output voltage ripple to the FB node. If the C_FF value is too large, it can couple too much ripple to the FB and affect V_OUT regulation. It could also couple too much transient voltage deviation and falsely trigger PGOOD flag.

7.3.11 Bootstrap Capacitor and V_BOOT-UVLO

The driver of the HS switch requires a bias voltage higher than the V_IN voltage. The capacitor, C_BOOT in 簡(jiǎn)化原理圖, connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (V_SW + V_CC). A boot diode is integrated on the die to minimize external component count. TI recommends a high-quality 0.47-µF, 6.3-V or higher voltage ceramic capacitor for C_BOOT. The V_{BOOT_UVLO} threshold is designed to maintain proper HS switch operation. If the C_BOOT is not charged above this voltage with respect to SW, the device initiates a charging sequence using the LS switch before turning on the HS switch.

7.3.12 Power-Good and Overvoltage Protection

The LM73605/6 has a built-in power-good (PGOOD) flag to indicate whether the output voltage is at an appropriate level or not. The PGOOD flag can be used for start-up sequencing of multiple rails. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate logic voltage (any voltage below 15 V). The pin can sink 5 mA of current and maintain its specified logic low level. A typical pullup resistor value is 10 kΩ to 100 kΩ. When the FB voltage is higher than V_PGOOD-OV or lower than V_PGOOD-UV threshold, the PGOOD internal switch is turned on, and the PGOOD pin voltage is pulled low. When the FB is within the range, the PGOOD switch is turned off, and the pin is pulled up to the voltage connected to the pullup resistor. The PGOOD function also have a deglitch timer for about 140 µs for each transition. If it is desired to pull up PGOOD pin to a voltage higher than 15 V, a resistor divider can be used to divide the voltage down.

Figure 24. Divider for PGOOD Pullup Voltage

With a given pullup voltage V_PU, select a desired voltage on the PGOOD pin, V_PG. With a selected R_PGT, the R_PGB can be found by:

Equation 22.

When the device is disabled, the output voltage is low, and the PGOOD flag indicates logic low as long as V_IN > 2 V.

7.3.13 Overcurrent and Short-Circuit Protection

The LM73605/6 is protected from overcurrent conditions with cycle-by-cycle current limiting on both HS and LS MOSFETs.

The HS switch is turned off when HS current goes beyond the peak current limit, I_HS-LIMIT. The LS switch can only be turned off when LS current is below LS current limit, I_LS-LIMIT. If the LS switch current is higher than I_LS-LIMIT at the end of a switching cycle, the switching cycle is extended until the LS current reduces below the limit.

Current limiting on both HS and LS switches provides tighter control of the maximum DC inductor current, or output current. They also help prevent runaway current at extreme conditions. With LM73605/6, the maximum output current is always limited at

The LM73605/6 employs hiccup current protection at extreme overload conditions, including short-circuit condition. Hiccup is only activated when V_OUT droops below 40% (typical) of the regulation voltage and stays below for 128 consecutive switching cycles. Under overcurrent conditions when V_OUT has not fallen below 40% of regulation, the LM73605/6 continues operation with cycle-by-cycle HS and LS current limiting.

Hiccup is disabled during soft-start. When hiccup is triggered, the device turns off V_OUT regulation and re-tries soft start after a re-try delay time, T_OC = 46 ms (typical). The long wait time allows the device, and the load, to cool down under such fault conditions. If the fault condition still exists when re-try, hiccup shuts down the device and repeats the wait and re-try cycle. If the fault condition has been removed, the device starts up normally.

If tracking was used for initial sequencing, the device restarts using the internal soft-start ramp. Hiccup mode helps to reduce the device power dissipation and die temperature under severe overcurrent conditions and short circuits. It improves system reliability and prolongs the life span of the device.

In FPWM mode, negative current protection is implemented to protect the switches from extreme negative currents. When LS switch current reaches I_NEG-LIMIT, LS switch turns off, and HS switch turns on to conduct the negative current. HS switch is turned off once its current reaches 0 A.

7.3.14 Thermal Shutdown

Thermal shutdown protection prevents the device from extreme junction temperature. The device is turned off when the junction temperature exceeds 160°C (typical). After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature drops to approximately 135°C. When the junction temperature falls below 135°C, the LM73605/6 restarts.

7.4.1 Shutdown Mode

The EN pin provides electrical on/off control of the device. When the EN pin voltage is below V_{EN_VCC_L}, the device is in shutdown mode. The LDO output voltage V_CC = 0 V and the output voltage V_OUT = 0 V. In shutdown mode the quiescent current drops to a very low value.

7.4.2 Standby Mode

The internal LDO has a lower EN threshold than that required to start the regulator. When the EN pin voltage is above V_{EN_VCC_H}, the internal LDO regulates the VCC voltage. The precision enable circuitry is turned on once V_CC is above V_{CC_UVLO}. The device is in standby mode if EN voltage is below V_{EN_VOUT_H}. The internal MOSFETs remains in tri-state unless the voltage on EN pin goes beyond V_{EN_VOUT_H} threshold. The LM73605/6 also employs UVLO protection. If the VCC voltage is below the V_{CC_UVLO} level, the output of the regulator is turned off.

7.4.3 Active Mode

The LM73605/6 is in active mode when the EN voltage is above V_{EN_VOUT_H}, and V_CC is above V_{CC_UVLO}. The simplest way to enable the operation of the LM73605/6 is to pull up the EN pin to PVIN, which allows self-start-up when the input voltage ramps up.

In active mode, depending on the load current and mode setting, the LM73605/6 is in one of four modes:

1. CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple;
2. DCM with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current ripple in CCM operation;
3. PFM when switching frequency is decreased at very light load;
4. Under overcurrent or overtemperature conditions, the device operates in one of the fault protection modes.

See Table 2 for mode-setting details.