Table 4. Design Example Parameters

8.2.2.1 Custom Design With WEBENCH® Tools

To create a custom design with the WEBENCH® Power Designer, click the LM73605 or LM73606 device.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Setpoint

The output voltage of the LM73605/6 device is externally adjustable using a resistor divider network. The divider network is comprised of top feedback resistor R_FBT and bottom feedback resistor R_FBB. Use Equation 24 to determine the output voltage of the converter.

Equation 24.

Typically, R_FBT = 10 kΩ to 100 kΩ is recommended. Larger R_FBT and R_FBB values reduce the quiescent current going through the divider, which help maintain high efficiency at very light loads. But larger divider values also make the feedback path more susceptible to noise. If efficiency at very light loads is critical in a certain application, R_FBT up to 1 MΩ can be used.

Equation 25.

R_FBT = 100 kΩ is selected here. R_FBB = 24.99 kΩ can be calculated to get 5-V output voltage.

8.2.2.3 Switching Frequency

The default switching frequency of the LM73605/6 device is set at 500 kHz. For this design, the RT pin can be floating, and the LM73605/6 switches at 500 kHz in CCM mode. An R_T resistor of 78.7 kΩ, calculated using Equation 13, Figure 21, or Table 1, can be connected from RT pin to ground to obtain 500-kHz operation frequency as well.

The LM73605/6 switching action can synchronize to an external clock from 350 kHz to 2.2 MHz. TI recommends connecting an external clock to the SYNC/MODE pin with a 50-Ω to 100-Ω termination resistor. The SYNC/MODE pin must be grounded if not used.

RT pin is floating and SYNC/MODE pin is tied to ground in this design.

8.2.2.4 Input Capacitors

The LM73605/6 device requires high-frequency ceramic input decoupling capacitors. Depending on the application, a bulk input capacitor can also be added. The typical recommended ceramic decoupling capacitors include one small, 0.1 µF to 1 µF, and one large, 10 µF to 22 µF, capacitors. TI recommends high-quality ceramic type X5R or X7R capacitors. The voltage rating must be greater than the maximum input voltage. As a general rule, to compensate the derating TI recommends a voltage rating of twice the maximum input voltage.

It is very important in buck regulator to place the small decoupling capacitor right next to the PVIN and PGND pins. This capacitor is used to bypass the high frequency switching noise by providing a return path of the noise. It prevents the noise from spreading to wider area of the board. The large bypass ceramic capacitor must also be as close as possible to the PVIN and PGND pins.

Additionally, some bulk capacitance may be required, especially if the LM73605/6 circuit is not located within approximately 2 inches from the input voltage source. This capacitor is used to provide damping to the voltage spike due to the lead inductance of the cable. The optimum value for this capacitor is four times the ceramic input capacitance with ESR close to the characteristic impedance of the LC filter formed by your input inductance and your ceramic input capacitors. It is not critical that the electrolytic filter be at the optimum value for damping, but it must be rated to handle the maximum input voltage including ripple voltage.

For this design, two 10-µF, X7R dielectric capacitors rated for 50 V are used for the input decoupling capacitance, and a capacitor with a value of 0.47 µF for high-frequency filtering.

8.2.2.5 Inductor Selection

The first criterion for selecting an output inductor is the inductance. In most buck converters, this value is based on the desired peak-to-peak ripple current in the inductor, I_Lripple. An inductance that gives a ripple current of 10% to 30% of the maximum output current (5 A or 6 A) is a good starting point. The inductance can be calculated from Equation 26:

Equation 26.

where

• I_Lripple = (0.1 to 0.3) × I_{L_MAX}
• I_{L_MAX} = 5 A for LM73605 and 6 A for LM73606
• D = V_OUT / V_IN

Selected I_Lripple is between 10% to 30% of the rated current of the device.

As with switching frequency, the selection of the inductor is a tradeoff between size, cost, and performance. Higher inductance gives lower ripple current and hence lower output voltage ripple. With peak current mode control, the current ripple is the input signal to the control loop. A certain amount of ripple current is needed to maintain the signal-to-noise ratio of the control loop. Within the same series (same size/height), a larger inductance will have a higher series resistance (ESR). With similar ESR, size and/or height will be greater. Larger inductance also has slower current slew rate during large load transients.

Lower inductance usually results in a smaller, less expensive component; however, the current ripple will be higher, thus more output capacitor is needed to maintain the same amount of output voltage ripple. The RMS current is higher with the same load current due to larger ripple. The switching loss is higher because the switch current, which is the peak current, is higher when the HS switch turns off and LS switch turns on. Core loss of the inductor is also larger with higher ripple. Core loss needs to be considered, especially with higher switching frequencies. Check the ripple current over V_{IN_MIN} to V_{IN_MAX} range to make sure current ripple is reasonable over entire supply voltage range.

For applications with large V_OUT and typical V_OUT / V_IN > 50%, sub-harmonic oscillation can be a concern in peak current-mode-controlled buck converters. Select inductance so that

The second criterion is inductor saturation current rating. Because the maximum inductor current is limited by the high-side switch current limit, it is advised to select an inductor with a saturation current higher than the I_LIMIT-HS. TI recommends selection of soft saturation inductors. A power inductor could be the major source of radiated noise. When EMI is a concern in the application, select a shielded inductor, if possible.

For this design, 20% ripple of 5 A yields 5.8-µH inductance. A 4.7-µH inductor is selected, which gives 25% ripple current.

8.2.2.6 Output Capacitor Selection

The output capacitor is responsible for filtering the inductor current, and supplying load current during transients. Capacitor selection depends on application conditions as well as ripple and transient requirements. Best performance is achieved by using ceramic capacitors or combinations of ceramic and other types of capacitors. For high output voltage conditions, such as 12 V and above, finding ceramic capacitors that are rated for an appropriate voltage becomes challenging. In such cases choose a low-ESR SP-CAP™ or POSCAP™-type capacitor. It is a good idea to use a low-value ceramic capacitor in parallel with other capacitors, to bypass high frequency noise between ground and V_OUT.

For a given input and output requirement, Equation 28 gives an approximation for a minimum output capacitor required.

Equation 28.

where

• r = Ripple ratio of the inductor ripple current (I_Lripple / 5 A or 6 A)
• ΔV_OUT = Target output voltage undershoot, for example, 5% to 10% of V_OUT
• D’ = 1 – duty cycle
• f_SW = switching frequency
• I_OUT = load current

Along with Equation 28, for the same requirement calculate the maximum ESR with Equation 29.

Equation 29.

The output capacitor is also the dominating factor in the loop response of a peak-current mode controlled buck converter. A simplified estimation of the control loop crossover frequency can be found by Equation 18.

Select C_OUT so that the f_X is no higher than 1/6 of the switching frequency. Typically, f_X / f_SW = 1/10 to 1/8 provides a good combination of stability and performance.

For this design, one 0.47-µF, 50-V X7R and four 22-µF, 16-V, X7R ceramic capacitors are used in parallel.

8.2.2.7 Feed-Forward Capacitor

The LM73605/6 is internally compensated. Typically, select R_FBT ≤ 100 kΩ, then C_FF is not needed. When very low quiescent current is needed, R_FBT = 1 MΩ may be used. If C_OUT is mainly ceramic type low ESR capacitors, an external feed-forward capacitor C_FF may be needed to improve the phase margin. Add C_FF in parallel with R_FBT. C_FF is chosen such that the phase boost is maximized at the estimated crossover frequency f_X. Equation 21 was tested.

With this design, because R_FBT = 100 kΩ is selected, no C_FF is needed.

8.2.2.8 Bootstrap Capacitors

Every LM73605/6 design requires a bootstrap capacitor, C_BOOT. The recommended bootstrap capacitor is 0.47 µF and rated at 6.3 V or greater. The bootstrap capacitor is located between the SW pin and the CBOOT pin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.

8.2.2.9 VCC Capacitor

The VCC pin is the output of an internal LDO for LM73605/6. The input for this LDO comes from either V_IN or BIAS pin voltage. The recommended C_VCC capacitor is 2.2 µF and rated at 6.3 V or greater. It must be a high-quality ceramic type with X7R or X5R grade to insure stability. Never short VCC pin to ground during operation.

8.2.2.10 BIAS

Because V_OUT = 5 V in this design, the BIAS pin is tied to V_OUT to reduce LDO power loss. The output voltage is supplying the LDO current instead of the input voltage. The power saving is I_LDO × (V_IN – V_OUT). The power saving is more significant when V_IN >> V_OUT and with higher frequency operation. To prevent V_OUT noise and transients from coupling to BIAS, a series resistor, 1 Ω to 10 Ω, may be added between V_OUT and BIAS. A bypass capacitor with a value of 1 μF or higher can be added close to the BIAS pin to filter noise.

8.2.2.11 Soft Start

The SS/TRK pin can be floating to start up following the internal soft-start ramp. In order to extend the soft-start time, an external soft-start capacitor can be used. Use Equation 12 in order to calculate the soft-start capacitor value.

With a desired soft-start time t_SS = 11 ms, a soft-start charging current of I_SSC = 2 µA (typical), and V_FB = 1.006 V (typical), Equation 12 yields a soft-start capacitor value of 22 nF.

8.2.2.12 Undervoltage Lockout Setpoint

The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENT and R_ENB. With one selected R_ENT value, R_ENB can be found by Equation 10.

Note that the divider adds to supply quiescent current by V_IN / (R_ENT + R_ENB). Small R_ENT and R_ENB values add more quiescent current loss. However, large divider values make the node more sensitive to noise.

In this design, EN pin is tied to PVIN pin with a 100-kΩ resistor.

8.2.2.13 PGOOD

For this design, a 100-kΩ resistor is used to pull up PGOOD to V_OUT.