ZHCSM29A September 2023 – June 2024 LM70840-Q1 , LM70860-Q1 , LM70880-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 說明（續(xù)）
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Input Voltage Range (VIN)
- 7.3.2 High-Voltage Bias Supply Regulator (VCC, BIAS, VDDA)
- 7.3.3 Enable (EN)
- 7.3.4 Power-Good Monitor (PG)
- 7.3.5 Switching Frequency (RT)
- 7.3.6 Dual Random Spread Spectrum (DRSS)
- 7.3.7 Soft Start
- 7.3.8 Output Voltage Setpoint (FB)
- 7.3.9 Minimum Controllable On-Time
- 7.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
- 7.3.11 Slope Compensation
- 7.3.12 Shunt Current Sensing
- 7.3.13 Hiccup Mode Current Limiting
- 7.3.14 Device Configuration (CONFIG)
- 7.3.15 Single-Output Dual-phase Operation
- 7.3.16 Pulse Frequency Modulation (PFM) / Synchronization
- 7.3.17 Thermal Shutdown (TSD)
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Design 1 – High Efficiency, Wide Input, 400-kHz Synchronous
Buck Regulator
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Custom Design With WEBENCH? Tools
- 8.2.1.2.2 Custom Design With Excel Quickstart Tool
- 8.2.1.2.3 Buck Inductor
- 8.2.1.2.4 Current-Sense Resistance
- 8.2.1.2.5 Output Capacitors
- 8.2.1.2.6 Input Capacitors
- 8.2.1.2.7 Frequency Set Resistor
- 8.2.1.2.8 Feedback Resistors
- 8.2.1.2.9 Compensation Components
- 8.2.1.3 Application Curves
- 8.2.2 Design 2 – High Efficiency 48V to 12V 400kHz Synchronous Buck Regulator
- 8.2.1
Design 1 – High Efficiency, Wide Input, 400-kHz Synchronous
Buck Regulator
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RRX|29
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.3.14 Device Configuration (CONFIG)
The LM708x0-Q1 can be configured for operation in Standalone Mode (single device) or for operation in single output interleaved mode (two devices) for paralleling the outputs of two devices for high-current applications. When operating in interleaved mode, one of the two devices has to be configured as a primary device while the other device has to be configured as a secondary device. There is also the option to enable or disable the DRSS function as detailed in Table 7-2.
During device startup, the CONFIG pin is sampled and latched. The configuration cannot be changed "on the fly". The LM708x0-Q1 input voltage must be recycled or EN pin toggled before the device can be reconfigured. Figure 7-5 shows the configuration timing diagram.
When the DRSS function is enabled, the LM708x0-Q1 cannot be synchronized to an external clock.
| RCONFIG | Mode | Function | DRSS |
|---|---|---|---|
| 29.4kΩ | Standalone | N/A | Disabled |
| 41.2kΩ | Standalone | N/A | Enabled |
| 54.9kΩ | Interleaved | Primary | Disabled |
| 71.5kΩ | Interleaved | Primary | Enabled |
| 90.9kΩ | Interleaved | Secondary | N/A |
Figure 7-5 Configuration Timing