6 Pin Configuration and Functions

Connect the exposed pad to AGND and PGND on the PCB.

Figure 6-1 24-Pin VQFN RGY Package with Wettable Flanks(Top View)

Table 6-1 Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NO.	NAME	I/O⁽¹⁾	DESCRIPTION
1	AVSS	G	Active EMI bias ground connection
2	INJ	O	Active EMI injection output
3	CNFG	1	Connect a resistor to ground to set primary/secondary, spread spectrum enable/disable, or interleaved operation. After start-up, use CNFG to enable AEF.
4	RT	I	Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100 kHz and 2.2 MHz.
5	EXTCOMP	O	The output of the transconductance error amplifier. If used, connect the compensation network from EXTCOMP to AGND.
6	FB	I	Connect FB to VDDA to set the output voltage to 3.3 V. Connect FB using a 24.9 kΩ or 49.9 kΩ to VDDA to set the output voltage to 5 V or 12 V, respectively. Install a resistor divider from VOUT to AGND to set the output voltage setpoint between 0.8 V and 55 V. The regulation voltage at FB is 0.8 V.
7	AGND	G	Analog ground connection. Ground return for the internal voltage reference and analog circuits.
8	VDDA	O	Internal analog bias regulator. Connect a ceramic decoupling capacitor from VDDA to AGND.
9	VCC	P	VCC bias supply pin. Connect ceramic capacitors between VCC and PGND.
10	PGND	G	Power ground connection pin for low-side power MOSEFT gate driver
11	LO	O	Low-side power MOSFET gate driver output
12	VIN	P	Supply voltage input source for the VCC regulators
13	HO	O	High-side power MOSFET gate driver output
14	SW	P	Switching node of the buck regulator and high-side gate driver return. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
15	CBOOT	P	High-side driver supply for bootstrap gate drive
16	VCCX	P	Optional input for an external bias supply. If V_VCCX > 4.3 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled.
17	PG/SYNCOUT	P	An open-collector output that goes low if V_OUT is outside the specified regulation window. The PG/SYNCOUT pin of the primary controller in dual-phase mode provides a 180° phase-shifted SYNCOUT signal.
18	PFM/SYNC	I	Connect PFM/SYNC to VDDA to enable diode emulation mode. Connect PFM to GND to operate the LM5149-Q1 in forced PWM (FPWM) mode with continuous conduction at light loads. PFM/SYNC can also be used as a synchronization input to synchronize the internal oscillator to an external clock.
19	EN	I	An active-high precision input with rising threshold of 1 V and hysteresis current of 10 μA. If the EN voltage is less than 0.5 V, the LM5149-Q1 is in shutdown mode, unless a SYNC signal is present on PFM/SYNC.
20	ISNS+	I	Current sense amplifier input. Connect the ISNS+ to the inductor side of the external current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a Kelvin connection.
21	VOUT	I	Output voltage sense and the current sense amplifier input. Connect VOUT to the output side of the current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used).
22	AEFVDDA	P	Active EMI bias power. Connect a ceramic capacitor between AEFVDDA and AVSS.
23	SENSE	I	Active EMI sense input
24	REFAGND	G	Active EMI reference ground

(1) P = Power, G = Ground, I = Input, O = Output