ZHCSGB0B November 2017 – November 2020 LM5145
PRODUCTION DATA
The schematic diagram of a 300-kHz, 24-V nominal input, 10-A regulator powering a KeyStone? DSP is given in Figure 9-46. This high step-down ratio design leverages the low 40-ns minimum controllable on-time of the LM5145 controller to achieve stable, efficient operation at very low duty cycles. 60-V power MOSFETs, such as TI's CSD18543Q3A and CSD18531Q5A NexFET devices, are used together with a low-DCR, metal-powder inductor, and ceramic output capacitor implementation. An external rail between 8 V and 13 V powers VCC to minimize bias power dissipation, and a blocking diode connected to the VIN pin is used as recommended in Figure 8-2.
The important components for this design are listed in Table 9-12.
| REFERENCE DESIGNATOR | QTY | SPECIFICATION | MANUFACTURER | PART NUMBER |
|---|---|---|---|---|
| CIN | 5 | 2.2 μF, 100 V, X7R, 1206, ceramic | Murata | GRM31CR72A225MA73L |
| Samsung | CL31B225KCHSNNE | |||
| 3 | 4.7 μF, 80 V, X7R, 1210, ceramic | Murata | GRM32ER71K475KE14L | |
| COUT | 4 | 100 μF, 6.3V, X7S, 1210, ceramic | Murata | GRM32EC70J107ME15L |
| Taiyo Yuden | JMK325AC7107MM-P | |||
| 100 μF, 6.3V, X5R, 1206, ceramic | Murata | GRM31CR60J107ME39K | ||
| TDK | C3216X5R0J107M | |||
| Würth Electronik | 885012108005 | |||
| LF | 1 | 1 μH, 5.6 mΩ, 16 A, 6.95 × 6.6 × 2.8 mm | Cyntec | CMLE063T-1R0MS |
| 1 μH, 5.5 mΩ, 12 A, 6.65 × 6.45 × 3.0 mm | Würth Electronik | WE XHMI 74439344010 | ||
| 1 μH, 7.9 mΩ, 16 A, 6.5 × 6.0 × 3.0 mm | Panasonic | ETQP3M1R0YFN | ||
| 1 μH, 6.95 mΩ, 18 A, 6.76 × 6.56 × 3.1 mm | Coilcraft | XEL6030-102ME | ||
| Q1 | 1 | 60 V, 8.5 mΩ, high-side MOSFET, SON 3 × 3 | Texas Instruments | CSD18543Q3A |
| Q2 | 1 | 60 V, 4 mΩ, low-side MOSFET, SON 5 × 6 | Texas Instruments | CSD18531Q5A |
| U1 | 1 | Wide VIN synchronous buck controller | Texas Instruments | LM5145RGYR |
| U2 | 1 | 6- or 4-bit VID voltage programmer, WSON-10 | Texas Instruments | LM10011SD |
| U3 | 1 | KeyStone? DSP | Texas Instruments | TMS320C667x |
The regulator output current requirements are dependent upon the baseline and activity power consumption of the DSP in a real-use case. While baseline power is highly dependent on voltage, temperature and DSP frequency, activity power relates to dynamic core utilization, DDR3 memory access, peripherals, and so on. To this end, the IDAC_OUT pin of the LM10011 connects to the LM5145 FB pin to allow continuous optimization of the core voltage. The SmartReflex-enabled DSP provides 6-bit information using the VCNTL open-drain I/Os to command the output voltage setpoint with 6.4-mV step resolution.(1)