ZHCSPC5 October 2022 LM51231-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY CURRENT(BIAS, VCC, VOUT) | ||||||
| IBIAS-SD | BIAS current in shutdown | VUVLO = 0 V, VOUT = 11.3 V | 2.5 | 5 | μA | |
| IBIAS-ACTIVE | BIAS current in active (Non-switching, VCC is supplied by BIAS) | VUVLO = 2.5 V, VTRK = 0.6 V | 1.22 | 1.52 | mA | |
| IBIAS-BYP | BIAS current in bypass mode | VUVLO = 2.5 V, VTRK = 0.25 V | 1.22 | 1.52 | mA | |
| IVOUT-SD | VOUT current in shutdown | VUVLO = 0 V, VOUT = 11.3 V | 1 | μA | ||
| IVOUT-BYP-DE | VOUT current in bypass mode | VUVLO = 2.5 V, VTRK = 0.25 V, VVOUT = 12 V, MODE = GND | 100 | 115 | μA | |
| IVOUT-BYP-FPWM | VOUT current in bypass mode | VUVLO = 2.5 V, VTRK = 0.25 V, VVOUT = 12 V, MODE = VCC | 240 | 276 | μA | |
| IVOUT-ACTIVE | VOUT current in active (Non-switching) (DE mode) | VUVLO = 2.5 V, VTRK = 0.6 V, MODE = GND | 90 | 105 | μA | |
| VOUT current in active (Non-switching), (FPWM) | VUVLO = 2.5 V, VTRK = 0.6 V, MODE = VCC | 240 | 276 | μA | ||
| IBATTERY-SD | Battery drain in shutdown | VUVLO = 0 V, VOUT = 11.3 V | 2.5 | 5 | μA | |
| IBATTERY-DE | Battery drain in bypass mode (DE mode) | VUVLO = 2.5 V, VTRK = 0.25 V, MODE = GND | 1.44 | 1.59 | mA | |
| IBATTERY-FPWM | Battery drain in bypass mode (FPWM) | VUVLO = 2.5 V, VTRK = 0.25 V, MODE = VCC | 1.58 | 1.74 | mA | |
| ENABLE, UVLO | ||||||
| VEN-RISING | Enable threshold | EN rising | 0.45 | 0.55 | 0.65 | V |
| VEN-FALLING | Enable threshold | EN falling | 0.35 | 0.45 | 0.55 | V |
| VEN-HYS | Enable hysteresis | EN falling | 55 | 90 | 130 | mV |
| IUVLO-HYS | UVLO pull-down hysteresis current | VUVLO = 0.7 V | 8 | 10 | 12 | μA |
| VUVLO-RISING | UVLO threshold | UVLO rising | 1.05 | 1.1 | 1.15 | V |
| VUVLO-FALLING | UVLO threshold | UVLO falling | 1.025 | 1.075 | 1.125 | V |
| VUVLO-HYS | UVLO hysteresis | UVLO falling | 25 | mV | ||
| SYNC/DITHER/VH | ||||||
| VSYNC-RISING | SYNC threshold/SYNC detection threshold | SYNC rising | 2 | V | ||
| VSYNC-FALLING | SYNC threshold | SYNC falling | 0.4 | V | ||
| Minimum SYNC pull up pulse width | 100 | ns | ||||
| IDITHER | Dither source/sink current | 16 | 21 | 26 | μA | |
| ΔfSW1 | fSW Modulation (Upper Limit) | 5% | ||||
| ΔfSW2 | fSW Modulation (Lower Limit) | -6% | ||||
| VDITHER-FALLING | Dither disable threshold | 0.65 | 0.75 | 0.85 | V | |
| VCC | ||||||
| VVCC-REG1 | VCC regulation | IVCC = 100 mA | 4.75 | 5 | 5.25 | V |
| VVCC-REG2 | VCC regulation | No load | 4.75 | 5 | 5.25 | V |
| VVCC-REG3 | VCC regulation during dropout | VBIAS = 3.8V, IVCC = 100 mA | 3.45 | V | ||
| VVCC-UVLO-RISING | VCC UVLO threshold | VCC rising | 3.55 | 3.65 | 3.75 | V |
| VVCC-UVLO-FALLING | VCC UVLO threshold | VCC falling | 3.2 | 3.3 | 3.4 | V |
| IVCC-CL | VCC sourcing current limit | VVCC = 4 V | 100 | mA | ||
| CONFIGURATION (MODE) | ||||||
| VMODE-RISING | FPWM mode threshold | MODE rising | 2.0 | V | ||
| VMODE-FALLING | Diode emulation mode threshold | MODE falling | 0.4 | V | ||
| RT | ||||||
| VRT | RT regulation | 0.5 | V | |||
| VREF, TRK, VOUT | ||||||
| VREF | VREF regulation target | 0.99 | 1 | 1.005 | V | |
| VOUT-REG | VOUT regulation target1 with resistor divider (lower VOUT range) | VREF resistor divider to make VTRK = 0.25 V, RVREF = 65 kΩ | 4.915 | 5 | 5.085 | V |
| VOUT-REG | VOUT regulation target2 with resistor divider (lower VOUT range) | VREF resistor divider to make VTRK = 0.5 V, RVREF = 65 kΩ | 9.9 | 10 | 10.1 | V |
| VOUT-REG | VOUT regulation target3 with resistor divider (lower VOUT range) | VREF resistor divider to make VTRK = 1.0 V, RVREF = 65 kΩ | 19.8 | 20 | 20.2 | V |
| VOUT-REG | VOUT regulation target4 with resistor divider (upper VOUT range) | VREF resistor divider to make VTRK = 0.25 V, RVREF = 35 kΩ | 14.74 | 15 | 15.24 | V |
| VOUT-REG | VOUT regulation target5 with resistor divider (upper VOUT range) | VREF resistor divider to make VTRK = 0.5 V, RVREF = 35 kΩ | 29.7 | 30 | 30.3 | V |
| VOUT-REG | VOUT regulation target6 with resistor divider (upper VOUT range) | VREF resistor divider to make VTRK = 0.95 V, RVREF = 35 kΩ | 56.43 | 57 | 57.57 | V |
| VOUT-REG | VOUT regulation target1 using TRK (lower VOUT range) | VTRK = 0.25 V, RVREF = 65 kΩ | 4.91 | 5 | 5.09 | V |
| VOUT-REG | VOUT regulation target2 using TRK (lower VOUT range) | VTRK = 0.5 V, RVREF = 65 kΩ | 9.88 | 10 | 10.11 | V |
| VOUT-REG | VOUT regulation target3 using TRK (lower VOUT range) | VTRK = 1.0 V, RVREF = 65 kΩ | 19.8 | 20 | 20.2 | V |
| VOUT-REG | VOUT regulation target4 using TRK (upper VOUT range) | VTRK = 0.25 V, RVREF = 35 kΩ | 14.71 | 15 | 15.25 | V |
| VOUT-REG | VOUT regulation target5 using TRK (upper VOUT range) | VTRK = 0.5 V, RVREF = 35 kΩ | 29.6 | 30 | 30.3 | V |
| VOUT-REG | VOUT regulation target6 using TRK (upper VOUT range) | VTRK = 0.95 V, RVREF = 35 kΩ | 56.45 | 57 | 57.5 | V |
| ITRK | TRK bias current | 1 | μA | |||
| SOFT START, DE to FPWM TRANSITION | ||||||
| ISS | Soft-start current | 17 | 20 | 23 | μA | |
| VSS-DONE | MODE transition start | SS rising | 1.3 | 1.5 | 1.7 | V |
| RSS | SS pull-down switch RDSON | 30 | 70 | Ω | ||
| VSS-DIS | SS discharge detection threshold | 30 | 50 | 75 | mV | |
| VSS-FB | internal SS to FB clamp | VFB=0V | 55 | 75 | mV | |
| CURRENT SENSE (CSP, CSN, SW, SENSE) | ||||||
| VSLOPE | Peak slope compensation amplitude | RT = 220 kΩ, Referenced to CS input | 45 | mV | ||
| ACS | Current sense amplifier gain | CSP=3.0V | 10 | V/V | ||
| Current sense amplifier gain | CSP=1.5V | 10 | V/V | |||
| VCLTH | Positive peak current limit threshold (CSP-CSN) | CSP=3.0V, MODE = GND | 52 | 60 | 68 | mV |
| Positive peak current limit threshold (CSP-CSN) | CSP=1.5V, MODE = GND | 51 | 60 | 72 | mV | |
| VZCD-DE | ZCD threshold (SW-SENSE) | MODE = GND | 4 | mV | ||
| VI-NEG-FPWM | Negative current limit threshold (SW-SENSE) | MODE = VCC | –150 | mV | ||
| VCS-FWD | Forward current threshold voltage to enter bypass mode (CSP-CSN) | VULVO = 2.5 V, VTRK = 0.25 V | 2 | 6 | 10 | mV |
| VZCD-BYP | Zero cross detection in bypass mode (DE mode) (SW-SENSE) | VULVO = 2.5 V, VTRK = 0.25 V, MODE = GND | -5 | mV | ||
| VI-NEG-BYP | Negative current limit in bypass mode (FPWM) (SW-SENSE) | VULVO = 2.5 V, VTRK = 0.25 V, MODE = VCC | -150 | mV | ||
| ICSN | CSN bias current | 1 | μA | |||
| ICSP | CSP bias current | 110 | μA | |||
| BOOT FAULT PROTECTION (HB) | ||||||
| Maximum replenish pulse cycles | 4 | cycles | ||||
| Replenish off cycles | 12 | cycles | ||||
| Number of sets to enter hiccup mode protection | 4 | sets | ||||
| Off-cycle during hiccup mode off | 512 | cycles | ||||
| ERROR AMPLIFIER (COMP) | ||||||
| Gm | Transconductance | 1 | mA/V | |||
| ISOURCE-MAX | Maximum COMP sourcing current | VCOMP=0V | 95 | μA | ||
| ISINK-MAX | Maximum COMP sinking current | VCOMP=1.8V | 90 | μA | ||
| VCLAMP-MAX | COMP maximum clamp voltage | COMP rising | 2.05 | 2.4 | 2.8 | V |
| VCLAMP-MIN | COMP minimum clamp voltage | COMP falling | 0.65 | V | ||
| PULSE WIDTH MODULATION (PWM) | ||||||
| fSW1 | Switching frequency | RT = 220 kΩ | 85 | 100 | 115 | kHz |
| fSW2 | Switching frequency | RT = 9.09 kΩ | 1980 | 2200 | 2420 | kHz |
| tON-MIN | Minimum controllable on-time | RT = 9.09 kΩ | 14 | 20 | 50 | ns |
| tOFF-MIN | Minimum forced off-time | RT = 9.09 kΩ | 70 | 95 | 115 | ns |
| DMAX1 | Maximum duty cycle limit | RT = 220kΩ | 90% | 94% | 98% | |
| DMAX2 | Maximum duty cycle limit | RT = 9.09 kΩ | 75% | 80% | 83% | |
| PGOOD, OVP | ||||||
| VOVTH-RISING | Overvoltage threshold (OVP threshold) | VOUT rising (referenced to VOUT-REG) | 108.5% | 110% | 113.5% | |
| VOVTH-FALLING | Overvoltage threshold (OVP threshold) | VOUT falling (referenced to VOUT-REG) | 100.5% | 103% | 105.5% | |
| VOVTH-DLY | Delay before entering bypass mode | 30 | us | |||
| VUVTH-RISING | Undervoltage threshold (PGOOD threshold) | VOUT rising (referenced to VOUT-REG) | 91.5% | 94% | 98% | |
| VUVTH-FALLING | Undervoltage threshold (PGOOD threshold) | VOUT falling (referenced to VOUT-REG) | 89.5% | 92% | 95.5% | |
| UV comparator deglitch filter | Rising edge | 26 | μs | |||
| UV comparator deglitch filter | Falling edge | 21 | μs | |||
| RPGOOD | PGOOD pull-down switch RDSON | 90 | 180 | Ω | ||
| Minimum BIAS for valid PGOOD | 2.5 | V | ||||
| MOSFET DRIVER | ||||||
| High-state voltage drop (HO driver) | 100mA sinking | 0.08 | 0.15 | V | ||
| Low-state voltage drop (HO driver) | 100mA sourcing | 0.04 | 0.1 | V | ||
| High-state voltage drop (LO driver) | 100mA sinking | 0.08 | 0.17 | V | ||
| Low-state voltage drop (LO driver) | 100mA sourcing | 0.04 | 0.1 | V | ||
| VHB-UVLO | HB-SW UVLO threshold | HB-SW falling | 2.2 | 2.5 | 3.0 | V |
| tDHL | HO off to LO on deadtime | 20 | ns | |||
| tDLH | LO off to HO on deadtime | 22 | ns | |||
| HB diode resistance | 1.2 | Ω | ||||
| ICP | HB charge pump current | BIAS=3.8V | 30 | 55 | μA | |
| THERMAL SHUTDOWN | ||||||
| TTSD-RISING | Thermal shutdown threshold | Temperature rising | 175 | °C | ||
| TTSD-HYS | Thermal shutdown hysteresis | 15 | °C | |||