ZHCSPC5 October 2022 LM51231-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Device Enable/Disable (EN, VH Pin)
- 7.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
- 7.3.3 Light Load Switching Mode Selection (MODE Pin)
- 7.3.4 VOUT Range Selection (RANGE Pin)
- 7.3.5 Line Undervoltage Lockout (UVLO Pin)
- 7.3.6 Fast Restart using VCC HOLD (VH Pin)
- 7.3.7 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
- 7.3.8 Overvoltage Protection (VOUT Pin)
- 7.3.9 Power Good Indicator (PGOOD Pin)
- 7.3.10 Dynamically Programmable Switching Frequency (RT)
- 7.3.11 External Clock Synchronization (SYNC Pin)
- 7.3.12 Programmable Spread Spectrum (DITHER Pin)
- 7.3.13 Programmable Soft-start (SS Pin)
- 7.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
- 7.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
- 7.3.16 Constant Peak Current Limit (CSP, CSN Pin)
- 7.3.17 Maximum Duty Cycle and Minimum Controllable On-time Limits
- 7.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
- 7.3.19 Thermal Shutdown Protection
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RGR|20
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RGR|20
訂購信息
7.3.1 Device Enable/Disable (EN, VH Pin)
The device shuts down when EN is less than the EN threshold (VEN) and VH is less than the SYNC threshold (VSYNC). The device is enabled when EN is greater than VEN or VH is greater than VSYNC. The VH pin provides a 40-μs internal delay before the device shuts down.
The device provides a 33-kΩ internal EN pulldown resistor to prevent a false turnon when the pin is floating. The EN pulldown resistor is connected to ground during the device configuration time or when the device shuts down. If the device configuration is finished and VH is greater than VSYNC, EN hysteresis is accomplished by disconnecting/connecting the resistor when EN is greater/less than VEN.
Figure 7-1 EN/UVLO Circuit