ZHCSPC5 October 2022 LM51231-Q1
PRODUCTION DATA
In FPWM switching operation, the device enters bypass mode when the OVP status is triggered for at least 30 μs (VOVTH-DLY) and VCSP-CSN is greater than 6 mV (VCS-FWD), indicating positive inductor current. To exit bypass mode the either the OVP status is cleared or VSW-SENSE is less than -150 mV (VI-NEG-BYP). Current flow from VLOAD to VSUPPLY can occur in bypass mode while operating in FPWM. Once the high-side FET is disabled, the device enters active mode. The proper conditions must be achieved to enter bypass mode again. See Table 7-2 for details on how the device enters and exits bypass mode.
| Conditions (1) | |
|---|---|
| Enter bypass mode | VVOUT >VTRK
*KFB*VOVTH_RISING
AND VCSP-CSN > VCS-FWD |
| Exit bypass mode | VVOUT < VTRK
*KFB*VOVTH_FALLING
OR VSW-SENSE < VI-NEG-BYP |