ZHCSCX2E January 2014 – October 2017 LM15851
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Signal Acquisition
- 7.3.2 The Analog Inputs
- 7.3.3 Clocking
- 7.3.4 Over-Range Function
- 7.3.5 ADC Core Features
- 7.3.6
Digital Down Converter (DDC)
- 7.3.6.1 NCO/Mixer
- 7.3.6.2 NCO Settings
- 7.3.6.3 Decimation Filters
- 7.3.6.4 DDC Output Data
- 7.3.6.5 Decimation Settings
- 7.3.7
Data Outputs
- 7.3.7.1 The Digital Outputs
- 7.3.7.2
JESD204B Interface Features and Settings
- 7.3.7.2.1 Scrambler Enable
- 7.3.7.2.2 Frames Per Multi-Frame (K-1)
- 7.3.7.2.3 DDR
- 7.3.7.2.4 JESD Enable
- 7.3.7.2.5 JESD Test Modes
- 7.3.7.2.6 Configurable Pre-Emphasis
- 7.3.7.2.7 Serial Output-Data Formatting
- 7.3.7.2.8 JESD204B Synchronization Features
- 7.3.7.2.9 SYSREF
- 7.3.7.2.10 SYNC~
- 7.3.7.2.11 Code-Group Synchronization
- 7.3.7.2.12 Multiple ADC Synchronization
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Map
- 7.6.1 Memory Map
- 7.6.2
Register Descriptions
- 7.6.2.1
Standard SPI-3.0 (0x000 to 0x00F)
- Table 34. Standard SPI-3.0 Registers
- 7.6.2.1.1 Configuration A Register (address = 0x000) [reset = 0x3C]
- 7.6.2.1.2 Configuration B Register (address = 0x001) [reset = 0x00]
- 7.6.2.1.3 Device Configuration Register (address = 0x002) [reset = 0x00]
- 7.6.2.1.4 Chip Type Register (address = 0x003) [reset = 0x03]
- 7.6.2.1.5 Chip Version Register (address = 0x006) [reset = 0x13]
- 7.6.2.1.6 Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
- 7.6.2.2 User SPI Configuration (0x010 to 0x01F)
- 7.6.2.3
General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
- 7.6.2.3.1 Power-On Reset Register (address = 0x021) [reset = 0x00]
- 7.6.2.3.2 I/O Gain 0 Register (address = 0x022) [reset = 0x40]
- 7.6.2.3.3 IO_GAIN_1 Register (address = 0x023) [reset = 0x00]
- 7.6.2.3.4 I/O Offset 0 Register (address = 0x025) [reset = 0x40]
- 7.6.2.3.5 I/O Offset 1 Register (address = 0x026) [reset = 0x00]
- 7.6.2.4
Clock (0x030 to 0x03F)
- 7.6.2.4.1 Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]
- 7.6.2.4.2 Clock Generator Status Register (address = 0x031) [reset = 0x07]
- 7.6.2.4.3 Clock Generator Control 2 Register (address = 0x032) [reset = 0x80]
- 7.6.2.4.4 Analog Miscellaneous Register (address = 0x033) [reset = 0xC3]
- 7.6.2.4.5 Input Clamp Enable Register (address = 0x034) [reset = 0x2F]
- 7.6.2.5 Serializer (0x040 to 0x04F)
- 7.6.2.6
ADC Calibration (0x050 to 0x1FF)
- 7.6.2.6.1 Calibration Configuration 0 Register (address = 0x050) [reset = 0x06]
- 7.6.2.6.2 Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4]
- 7.6.2.6.3 Calibration Background Control Register (address = 0x057) [reset = 0x10]
- 7.6.2.6.4 ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00]
- 7.6.2.6.5 Calibration Vectors Register (address = 0x05A) [reset = 0x00]
- 7.6.2.6.6 Calibration Status Register (address = 0x05B) [reset = undefined]
- 7.6.2.6.7 Timing Calibration Register (address = 0x066) [reset = 0x02]
- 7.6.2.7
Digital Down Converter and JESD204B (0x200-0x27F)
- 7.6.2.7.1 Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10]
- 7.6.2.7.2 JESD204B Control 1 Register (address = 0x201) [reset = 0x0F]
- 7.6.2.7.3 JESD204B Control 2 Register (address = 0x202) [reset = 0x00]
- 7.6.2.7.4 JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00]
- 7.6.2.7.5 JESD204B Control 3 Register (address = 0x204) [reset = 0x00]
- 7.6.2.7.6 JESD204B and System Status Register (address = 0x205) [reset = Undefined]
- 7.6.2.7.7 Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2]
- 7.6.2.7.8 Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB]
- 7.6.2.7.9 Overrange Period Register (address = 0x208) [reset = 0x00]
- 7.6.2.7.10 DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00]
- 7.6.2.7.11 DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00]
- 7.6.2.7.12 Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000]
- 7.6.2.7.13 NCO Frequency (Preset x) Register (address = see ) [reset = see ]
- 7.6.2.7.14 NCO Phase (Preset x) Register (address = see ) [reset = see ]
- 7.6.2.7.15 DDC Delay (Preset x) Register (address = see ) [reset = see ]
- 7.6.2.1
Standard SPI-3.0 (0x000 to 0x00F)
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
6.1 Absolute Maximum Ratings
The soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.(5)(1)(3)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Supply voltage | 1.2-V supply | VA12, VD12 | 1.4 | V | |
| 1.9-V supply | VA19 | 2.2 | |||
| 1.2-V supply difference between VA12 and VD12 | –200 | 200 | mV | ||
| Voltage | On any input pin (except VIN+ or VIN–) | –0.15 | V(VA19) + 0.15 | V | |
| On VIN+ or VIN– | 0 | 2 | |||
| Voltage difference | |(VIN+) – (VIN–)|(2) | 2 | V | ||
| |(DEVCLK+) – (DEVCLK–)| | 2 | ||||
| |(SYSREF+) – (SYSREF–)| | 2 | ||||
| |(~SYNC+) – (~SYNC–)| | 1 | ||||
| RF input power, PI | On VIN+, VIN–, with proper input common mode maintained. FIN ≥ 3 GHz, Z(SOURCE) = 100 Ω, Input_Clamp_EN = 0 or 1 | 11.07 | dBm | ||
| On VIN+, VIN–, with proper input common mode maintained. FIN = 1 GHz, Z(SOURCE) = 100 Ω, Input_Clamp_EN = 1 | 14.95 | ||||
| On VIN+, VIN–, with proper input common mode maintained. FIN ≤ 100 MHz, Z(SOURCE) = 100 Ω, Input_Clamp_EN = 1 | 20.97 | ||||
| Input current | At any pin other than VIN+ or VIN–(4) | –25 | 25 | mA | |
| VIN+ or VIN– | –50 | 50 | mA DC | ||
| Package(4) (sum of absolute value of all currents forced in or out, not including power supply current) | 100 | mA | |||
| Junction temperature, TJ | Power applied. Verified by High Temperature Operation Life testing to 1000 hours. | –40 | 150 | °C | |
| Storage temperature, Tstg | –65 | 150 | °C | ||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The analog inputs are protected as in the following circuit. Input-voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(4) When the input voltage at any pin (other than VIN+ or VIN–) exceeds the power supply limits (that is, less than GND or greater than VA19), the current at that pin must be limited to 25 mA. The 100-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies. This limit is not placed upon the power pins or thermal pad (GND).
(5) Reflow temperature profiles are different for lead-free and non-lead-free packages.