ZHCSCX2E January 2014 – October 2017 LM15851
PRODUCTION DATA.
See the JESD204B Synchronization Features section for more details.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LINK_UP | SYNC_STATUS | REALIGNED | ALIGNED | PLL_LOCKED | RESERVED | |
| R/W-0 | R/W-0 | R/W-X | R/W-X | R/W-0 | R/W-0 | R/W-00 | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0 | Always returns 0 |
| 6 | LINK_UP | R/W | 0 | When set, indicates that the JESD204B link is in the DATA_ENC state. |
| 5 | SYNC_STATUS | R/W | X | Returns the state of the JESD204B SYNC~ signal (SYNC_SE_N or SYNC_DIFF_N). 0 : SYNC~ asserted 1 : SYNC~ deasserted |
| 4 | REALIGNED | R/W | X | When high, indicates that the div8 clock, frame clock, or multiframe clock phase was realigned by SYSREF. Writing a 1 to this bit clears it. |
| 3 | ALIGNED | R/W | 0 | When high, indicates that the multiframe clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Writing a 1 to this bit clears it. |
| 2 | PLL_LOCKED | R/W | 0 | When high, indicates that the PLL is locked. |
| 1-0 | RESERVED | R/W | 0 | Always returns 0 |