ZHCSCX2E January 2014 – October 2017 LM15851
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Signal Acquisition
- 7.3.2 The Analog Inputs
- 7.3.3 Clocking
- 7.3.4 Over-Range Function
- 7.3.5 ADC Core Features
- 7.3.6
Digital Down Converter (DDC)
- 7.3.6.1 NCO/Mixer
- 7.3.6.2 NCO Settings
- 7.3.6.3 Decimation Filters
- 7.3.6.4 DDC Output Data
- 7.3.6.5 Decimation Settings
- 7.3.7
Data Outputs
- 7.3.7.1 The Digital Outputs
- 7.3.7.2
JESD204B Interface Features and Settings
- 7.3.7.2.1 Scrambler Enable
- 7.3.7.2.2 Frames Per Multi-Frame (K-1)
- 7.3.7.2.3 DDR
- 7.3.7.2.4 JESD Enable
- 7.3.7.2.5 JESD Test Modes
- 7.3.7.2.6 Configurable Pre-Emphasis
- 7.3.7.2.7 Serial Output-Data Formatting
- 7.3.7.2.8 JESD204B Synchronization Features
- 7.3.7.2.9 SYSREF
- 7.3.7.2.10 SYNC~
- 7.3.7.2.11 Code-Group Synchronization
- 7.3.7.2.12 Multiple ADC Synchronization
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Map
- 7.6.1 Memory Map
- 7.6.2
Register Descriptions
- 7.6.2.1
Standard SPI-3.0 (0x000 to 0x00F)
- Table 34. Standard SPI-3.0 Registers
- 7.6.2.1.1 Configuration A Register (address = 0x000) [reset = 0x3C]
- 7.6.2.1.2 Configuration B Register (address = 0x001) [reset = 0x00]
- 7.6.2.1.3 Device Configuration Register (address = 0x002) [reset = 0x00]
- 7.6.2.1.4 Chip Type Register (address = 0x003) [reset = 0x03]
- 7.6.2.1.5 Chip Version Register (address = 0x006) [reset = 0x13]
- 7.6.2.1.6 Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
- 7.6.2.2 User SPI Configuration (0x010 to 0x01F)
- 7.6.2.3
General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
- 7.6.2.3.1 Power-On Reset Register (address = 0x021) [reset = 0x00]
- 7.6.2.3.2 I/O Gain 0 Register (address = 0x022) [reset = 0x40]
- 7.6.2.3.3 IO_GAIN_1 Register (address = 0x023) [reset = 0x00]
- 7.6.2.3.4 I/O Offset 0 Register (address = 0x025) [reset = 0x40]
- 7.6.2.3.5 I/O Offset 1 Register (address = 0x026) [reset = 0x00]
- 7.6.2.4
Clock (0x030 to 0x03F)
- 7.6.2.4.1 Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]
- 7.6.2.4.2 Clock Generator Status Register (address = 0x031) [reset = 0x07]
- 7.6.2.4.3 Clock Generator Control 2 Register (address = 0x032) [reset = 0x80]
- 7.6.2.4.4 Analog Miscellaneous Register (address = 0x033) [reset = 0xC3]
- 7.6.2.4.5 Input Clamp Enable Register (address = 0x034) [reset = 0x2F]
- 7.6.2.5 Serializer (0x040 to 0x04F)
- 7.6.2.6
ADC Calibration (0x050 to 0x1FF)
- 7.6.2.6.1 Calibration Configuration 0 Register (address = 0x050) [reset = 0x06]
- 7.6.2.6.2 Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4]
- 7.6.2.6.3 Calibration Background Control Register (address = 0x057) [reset = 0x10]
- 7.6.2.6.4 ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00]
- 7.6.2.6.5 Calibration Vectors Register (address = 0x05A) [reset = 0x00]
- 7.6.2.6.6 Calibration Status Register (address = 0x05B) [reset = undefined]
- 7.6.2.6.7 Timing Calibration Register (address = 0x066) [reset = 0x02]
- 7.6.2.7
Digital Down Converter and JESD204B (0x200-0x27F)
- 7.6.2.7.1 Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10]
- 7.6.2.7.2 JESD204B Control 1 Register (address = 0x201) [reset = 0x0F]
- 7.6.2.7.3 JESD204B Control 2 Register (address = 0x202) [reset = 0x00]
- 7.6.2.7.4 JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00]
- 7.6.2.7.5 JESD204B Control 3 Register (address = 0x204) [reset = 0x00]
- 7.6.2.7.6 JESD204B and System Status Register (address = 0x205) [reset = Undefined]
- 7.6.2.7.7 Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2]
- 7.6.2.7.8 Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB]
- 7.6.2.7.9 Overrange Period Register (address = 0x208) [reset = 0x00]
- 7.6.2.7.10 DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00]
- 7.6.2.7.11 DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00]
- 7.6.2.7.12 Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000]
- 7.6.2.7.13 NCO Frequency (Preset x) Register (address = see ) [reset = see ]
- 7.6.2.7.14 NCO Phase (Preset x) Register (address = see ) [reset = see ]
- 7.6.2.7.15 DDC Delay (Preset x) Register (address = see ) [reset = see ]
- 7.6.2.1
Standard SPI-3.0 (0x000 to 0x00F)
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- NKE|68
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
7.3.3 Clocking
The LM15851device has a differential clock input, DEVCLK+ and DEVCLK–, that must be driven with an AC-coupled differential clock-signal. The clock inputs are internally terminated and biased. The input clock signal must be capacitively coupled to the clock pins as shown in Figure 33.
Figure 33. Differential Sample-Clock ConnectionThe differential sample-clock line pair must have a characteristic impedance of 100 Ω and must be terminated at the clock source of that 100-Ω characteristic impedance. The input clock line must be as short and direct as possible. The LM15851 clock input is internally terminated with an untrimmed 100-Ω resistance.
Insufficient input clock levels results in poor dynamic performance. Excessively-high input-clock levels can cause a change in the analog-input offset voltage. To avoid these issues, maintain the input clock level within the range specified in the Electrical Characteristics table.
The low times and high times of the input clock signal can affect the performance of any ADC. The LM15851device features a duty-cycle clock-correction circuit which maintains performance over temperature. The ADC meets the performance specification when the input clock high times and low times are maintained as specified in the Electrical Characteristics table.
High-speed high-performance ADCs such as the LM15851device require a very-stable input clock-signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution or ENOB (effective number of bits), maximum ADC input frequency, and the input signal amplitude relative to the ADC input full-scale range. Use Equation 1 to calculate the maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR.
where
- RMStot(J) is the RMS total of all jitter sources in seconds
- VI(PP) is the peak-to-peak analog input signal
- VFSR is the full-scale range of the ADC
- n is the ADC resolution in bits
- FIN is the maximum input frequency, in Hertz, at the ADC analog input
Note that the maximum jitter previously described is the root sum square (RSS) of the jitter from all sources, including that from the clock source, the jitter added by noise coupling at board level and that added internally by the ADC clock circuitry, in addition to any jitter added to the input signal. Because the effective jitter added by the ADC is beyond user control, the best option is to minimize the jitter from the clock source, the sum of the externally-added input clock jitter and the jitter added by any circuitry to the analog signal.
Input clock amplitudes above those specified in the Recommended Operating Conditions table can result in increased input-offset voltage. Increased input-offset voltage causes the converter to produce an output code other than the expected 2048 when both input pins are at the same potential.