ZHCSLW9 November 2022 ISOW7741-Q1 , ISOW7742-Q1
PRODUCTION DATA
To design with this device, use the parameters listed in Table 10-1.
| PARAMETER | VALUE |
|---|---|
| VDD input voltage | 3 V to 5.5 V |
| VIO input voltage | 1.71 V to 5.5 V |
| VISOIN input voltage | 1.71 V to 5.5 V |
| VDD decoupling capacitors | 10 μF + 1 μF + 0.01 μF + optional additional capacitance |
| VIO decoupling capacitors | 0.1 μF + optional additional capacitance |
| VISOIN decoupling capacitors | 0.1 μF + optional additional capacitance |
| VISOOUT decoupling capacitors | 10 μF + 1 μF + 0.01 μF + optional additional capacitance |
| VISOOUT to VISOIN series inductor | BLM15ELX9331SN1D |
| GND2 to GISOIN series inductor | BLM15ELX9331SN1D |
| VIO series inductor | BLM15ELX9331SN1D |
| VDD series inductor | BLM15ELX9331SN1D |
| GND1 to GNDIO series inductor | BLM15ELX9331SN1D |
Because of very-high current flowing through the ISOW7741-Q1 device device VDD and VISOOUT supplies, higher decoupling capacitors typically provide better noise and ripple performance. Although a 10-μF capacitor is adequate, higher decoupling capacitors (such as 47 μF) on both the VDD and VISOOUT pins to the respective grounds are strongly recommended to achieve the best performance.