ZHCSDR2A April 2015 – October 2024 FDC1004-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Detailed Description
- 7 Applications and Implementation
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
5.7 I2C Interface Timing
Over recommended operating free-air temperature range, VDD = 3.3V, for TA = TJ = 25°C (unless otherwise noted).
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| fSCL | Clock frequency(1) | 10 | 400 | kHz | ||
| tLOW | Clock low time(1) | 1.3 | μs | |||
| tHIGH | Clock high time(1) | 0.6 | μs | |||
| tHD;STA | Hold time (repeated) START condition(1) | After this period, the first clock pulse is generated | 0.6 | μs | ||
| tSU;STA | Set-up time for a repeated START condition(1) | 0.6 | μs | |||
| tHD;DAT | Data hold time(1)(2) | 0 | ns | |||
| tSU;DAT | Data setup time(1) | 100 | ns | |||
| tf | SDA fall time(1) | IL ≤ 3mA; CL ≤ 400pF | 300 | ns | ||
| tSU;STO | Set-up time for STOP condition(1) | 0.6 | μs | |||
| tBUF | Bus free time between a STOP and START condition(1) | 1.3 | μs | |||
| tVD;DAT | Data valid time(1) | 0.9 | ns | |||
| tVD;ACK | Data valid acknowledge time(1) | 0.9 | ns | |||
| tSP | Pulse width of spikes that must be suppressed by the input filter(1) | 50 | ns | |||
(1) This parameter is specified by design and/or characterization and is not tested in production.
(2) The FDC1004-Q1 provides an internal 300ns minimum hold time to bridge the undefined region of the falling edge of SCL.
Figure 5-1 I2C Timing