ZHCSDR2A April 2015 – October 2024 FDC1004-Q1
PRODUCTION DATA
The capacitive offset can be due to many factors including the initial capacitance of the sensor, parasitic capacitances of board traces, and the capacitance of any other connections between the sensor and the FDC.
The parasitic capacitances of the FDC1004-Q1 are calibrated out at production. If there are other sources of offset in the system, it can be necessary to calibrate the system capacitance offset in the application. Any offset in the capacitance input larger than ? LSB of the CAPDAC should first be removed using the on-chip CAPDACs. Any residual offset of approximately 1pF can then be removed by using the capacitance offset calibration register. The offset calibration register is reloaded by the default value at power-on or after reset. Therefore, if the offset calibration is not repeated after each system power-up, the calibration coefficient value should be stored by the host controller and reloaded as part of the FDC1004-Q1 setup.