ZHCSIO8 August 2018 DS90UH949A-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 DC Electrical Characteristics
- 6.6 AC Electrical Characteristics
- 6.7 DC and AC Serial Control Bus Characteristics
- 6.8 Recommended Timing for the Serial Control Bus
- 6.9 Timing Diagrams
- 6.10 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 High-Definition Multimedia Interface (HDMI)
- 7.3.2 Transition Minimized Differential Signaling
- 7.3.3 Enhanced Display Data Channel
- 7.3.4 Extended Display Identification Data (EDID)
- 7.3.5 Consumer Electronics Control (CEC)
- 7.3.6 +5-V Power Signal
- 7.3.7 Hot Plug Detect (HPD)
- 7.3.8 High-Speed Forward Channel Data Transfer
- 7.3.9 Back Channel Data Transfer
- 7.3.10 FPD-Link III Port Register Access
- 7.3.11 Power Down (PDB)
- 7.3.12 Serial Link Fault Detect
- 7.3.13 Interrupt Pin (INTB)
- 7.3.14 Remote Interrupt Pin (REM_INTB)
- 7.3.15 General-Purpose I/O
- 7.3.16 SPI Communication
- 7.3.17 Backward Compatibility
- 7.3.18 Audio Modes
- 7.3.19 HDCP
- 7.3.20 Built-In Self Test (BIST)
- 7.3.21 Internal Pattern Generation
- 7.3.22 Spread Spectrum Clock Tolerance
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 Serial Control Bus
- 7.5.2 Multi-Master Arbitration Support
- 7.5.3 I2C Restrictions on Multi-Master Operation
- 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
- 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
- 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
- 7.5.7 Prevention of I2C Faults During Abrupt System Faults
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.5.1 Serial Control Bus
This serializer may also be configured by the use of a I2C-compatible serial control bus. Multiple devices may share the serial control bus (up to 8 device addresses supported). The device address is set through a resistor divider (R1 and R2 — see Figure 21) connected to the IDx pin.
Figure 21. Serial Control Bus Connection The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to VDD18 or VDD33. For most applications, a 4.7-kΩ pullup resistor is recommended. However, the pullup resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low.
The IDx pin configures the control interface to one of 8 possible device addresses. A pullup resistor and a pulldown resistor may be used to set the appropriate voltage on the IDx input pin. See Table 10 for more information. 1% or 5% resistors can be used.
Table 9. Serial Control Bus Addresses for IDx
| NO. | RATIO
VR2 / VDD18 |
IDEAL VR2
(V) |
SUGGESTED RESISTOR R1 kΩ (1% tol) | SUGGESTED RESISTOR R2 kΩ (1% tol) | 7-BIT ADDRESS | 8-BIT ADDRESS |
|---|---|---|---|---|---|---|
| 1 | 0 | 0 | OPEN | Any value less than 100(1) | 0x0C | 0x18 |
| 2 | 0.208 | 0.374 | 118 | 30.9 | 0x0E | 0x1C |
| 3 | 0.323 | 0.582 | 107 | 51.1 | 0x10 | 0x20 |
| 4 | 0.440 | 0.792 | 113 | 88.7 | 0x12 | 0x24 |
| 5 | 0.553 | 0.995 | 82.5 | 102 | 0x14 | 0x28 |
| 6 | 0.668 | 1.202 | 68.1 | 137 | 0x16 | 0x2C |
| 7 | 0.789 | 1.420 | 56.2 | 210 | 0x18 | 0x30 |
| 8 | 1 | 1.8 | Any value less than 100(1) | OPEN | 0x1A | 0x34 |
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See Figure 22.
Figure 22. Start and Stop Conditions To communicate with an I2C slave, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address does not match a slave address of the device, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 23 and a WRITE is shown in Figure 24.
Figure 23. Serial Control Bus — Read 
Figure 24. Serial Control Bus — Write The I2C Master located at the serializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, refer to the TI Application Note I2C Communication Over FPD-Link III With Bidirectional Control Channel (SNLA131).