ZHCSIO8 August 2018 DS90UH949A-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 DC Electrical Characteristics
- 6.6 AC Electrical Characteristics
- 6.7 DC and AC Serial Control Bus Characteristics
- 6.8 Recommended Timing for the Serial Control Bus
- 6.9 Timing Diagrams
- 6.10 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 High-Definition Multimedia Interface (HDMI)
- 7.3.2 Transition Minimized Differential Signaling
- 7.3.3 Enhanced Display Data Channel
- 7.3.4 Extended Display Identification Data (EDID)
- 7.3.5 Consumer Electronics Control (CEC)
- 7.3.6 +5-V Power Signal
- 7.3.7 Hot Plug Detect (HPD)
- 7.3.8 High-Speed Forward Channel Data Transfer
- 7.3.9 Back Channel Data Transfer
- 7.3.10 FPD-Link III Port Register Access
- 7.3.11 Power Down (PDB)
- 7.3.12 Serial Link Fault Detect
- 7.3.13 Interrupt Pin (INTB)
- 7.3.14 Remote Interrupt Pin (REM_INTB)
- 7.3.15 General-Purpose I/O
- 7.3.16 SPI Communication
- 7.3.17 Backward Compatibility
- 7.3.18 Audio Modes
- 7.3.19 HDCP
- 7.3.20 Built-In Self Test (BIST)
- 7.3.21 Internal Pattern Generation
- 7.3.22 Spread Spectrum Clock Tolerance
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 Serial Control Bus
- 7.5.2 Multi-Master Arbitration Support
- 7.5.3 I2C Restrictions on Multi-Master Operation
- 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
- 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
- 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
- 7.5.7 Prevention of I2C Faults During Abrupt System Faults
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGC|64
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGC|64
訂購信息
7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
Configuration of the device may be done through the MODE_SEL[1:0] input pins, or through the configuration register bits. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the MODE_SEL[1:0] inputs. See Table 7 and Table 8. These values will be latched into register location during power-up:
Table 6. MODE_SEL[1:0] Settings
| MODE | SETTING | FUNCTION |
|---|---|---|
| EDID_SEL: Display ID Select | 0 | Look for remote EDID, if none found, use internal SRAM EDID. Can be overridden from register. Remote EDID address may be overridden from default 0xA0. |
| 1 | Use external local EDID. | |
| AUX_I2S: AUX Audio Channel | 0 | HDMI audio. |
| 1 | HDMI + AUX audio channel. | |
| EXT_CTL: External Controller Override | 0 | Internal HDCP/HDMI control. |
| 1 | External HDCP/HDMI control from I2C interface pins. | |
| COAX: Cable Type | 0 | Enable FPD-Link III for twisted pair cabling. |
| 1 | Enable FPD-Link III for coaxial cabling. | |
| REM_EDID_LOAD: Remote EDID Load | 0 | Use internal SRAM EDID. |
| 1 | If available, remote EDID is copied into internal SRAM EDID. |
Figure 20. MODE_SEL[1:0] Connection Diagram Table 7. Configuration Select (MODE_SEL0)
| NO. | RATIO
VR4/VDD18 |
TARGET VR4
(V) |
SUGGESTED RESISTOR PULLUP R3 kΩ (1% tol) | SUGGESTED RESISTOR PULLDOWN R4 kΩ (1% tol) | EDID_SEL | AUX_I2S |
|---|---|---|---|---|---|---|
| 1 | 0 | 0 | OPEN | Any value less than 100(1) | 0 | 0 |
| 2 | 0.208 | 0.374 | 118 | 30.9 | 0 | 1 |
| 3 | 0.553 | 0.995 | 82.5 | 102 | 1 | 0 |
| 4 | 0.668 | 1.202 | 68.1 | 137 | 1 | 1 |
(1) This resistor does not need to be 1% tolerance. 5% is acceptable.
Table 8. Configuration Select (MODE_SEL1)
| NO. | RATIO
VR6/VDD18 |
TARGET VR6
(V) |
SUGGESTED RESISTOR PULLUP R5 kΩ (1% tol) | SUGGESTED RESISTOR PULLDOWN R6 kΩ (1% tol) | EXT_CTL | COAX | REM_EDID_LOAD |
|---|---|---|---|---|---|---|---|
| 1 | 0 | 0 | OPEN | Any value less than 100(1) | 0 | 0 | 0 |
| 2 | 0.208 | 0.374 | 118 | 30.9 | 0 | 0 | 1 |
| 3 | 0.323 | 0.582 | 107 | 51.1 | 0 | 1 | 0 |
| 4 | 0.440 | 0.792 | 113 | 88.7 | 0 | 1 | 1 |
| 5 | 0.553 | 0.995 | 82.5 | 102 | 1 | 0 | 0 |
| 6 | 0.668 | 1.202 | 68.1 | 137 | 1 | 0 | 1 |
| 7 | 0.789 | 1.420 | 56.2 | 210 | 1 | 1 | 0 |
| 8 | 1 | 1.8 | Any value less than 100(1) | OPEN | 1 | 1 | 1 |
(1) This resistor does not need to be 1% tolerance. 5% is acceptable.
The strapped values can be viewed and/or modified in the following locations:
- EDID_SEL : Latched into BRIDGE_CTL[0], EDID_DISABLE (0x4F[0]).
- AUX_I2S : Latched into BRIDGE_CFG[1], AUDIO_MODE[1] (0x54[1]).
- EXT_CTL: Latched into BRIDGE_CFG[7], EXT_CONTROL (0x54[7]).
- COAX : Latched into DUAL_CTL1[7], COAX_MODE (0x5B[7]).
- REM_EDID_LOAD : Latched into BRIDGE_CFG[5] (0x54[5]).