ZHCSIO8 August 2018 DS90UH949A-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 DC Electrical Characteristics
- 6.6 AC Electrical Characteristics
- 6.7 DC and AC Serial Control Bus Characteristics
- 6.8 Recommended Timing for the Serial Control Bus
- 6.9 Timing Diagrams
- 6.10 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 High-Definition Multimedia Interface (HDMI)
- 7.3.2 Transition Minimized Differential Signaling
- 7.3.3 Enhanced Display Data Channel
- 7.3.4 Extended Display Identification Data (EDID)
- 7.3.5 Consumer Electronics Control (CEC)
- 7.3.6 +5-V Power Signal
- 7.3.7 Hot Plug Detect (HPD)
- 7.3.8 High-Speed Forward Channel Data Transfer
- 7.3.9 Back Channel Data Transfer
- 7.3.10 FPD-Link III Port Register Access
- 7.3.11 Power Down (PDB)
- 7.3.12 Serial Link Fault Detect
- 7.3.13 Interrupt Pin (INTB)
- 7.3.14 Remote Interrupt Pin (REM_INTB)
- 7.3.15 General-Purpose I/O
- 7.3.16 SPI Communication
- 7.3.17 Backward Compatibility
- 7.3.18 Audio Modes
- 7.3.19 HDCP
- 7.3.20 Built-In Self Test (BIST)
- 7.3.21 Internal Pattern Generation
- 7.3.22 Spread Spectrum Clock Tolerance
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 Serial Control Bus
- 7.5.2 Multi-Master Arbitration Support
- 7.5.3 I2C Restrictions on Multi-Master Operation
- 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
- 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
- 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
- 7.5.7 Prevention of I2C Faults During Abrupt System Faults
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
5 Pin Configuration and Functions
RGC Package
64-Pin VQFN
Top View
Pin Functions
| PIN | I/O, TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| HDMI TMDS INPUT | |||
| IN_CLK-
IN_CLK+ |
49
50 |
I, TMDS | TMDS Clock Differential Input |
| IN_D0-
IN_D0+ |
55
56 |
I, TMDS | TMDS Data Channel 0 Differential Input |
| IN_D1-
IN_D1+ |
59
60 |
I, TMDS | TMDS Data Channel 1 Differential Input |
| IN_D2-
IN_D2+ |
62
63 |
I, TMDS | TMDS Data Channel 2 Differential Input |
| OTHER HDMI | |||
| HPD | 42 | O, Open-Drain | Hot Plug Detect Output. Pull up to RX_5V with a 1-kΩ resistor |
| RX_5V | 43 | I | HDMI 5-V Detect Input |
| DDC_SDA | 44 | IO, Open-Drain | DDC Slave Serial Data
Pull up to RX_5V with a 47-kΩ resistor |
| DDC_SCL | 45 | I, Open-Drain | DDC Slave Serial Clock
Pull up to RX_5V with a 47-kΩ resistor |
| CEC | 1 | IO, Open-Drain | Consumer Electronic Control Channel Input/Output Interface.
Pullup with a 27-kΩ resistor to 3.3 V |
| X1 | 39 | I, LVCMOS | Optional Oscillator Input: This pin is the optional reference clock for CEC. It must be connected to a 25 MHz 0.1% (1000ppm), 45-55% duty cycle clock source at CMOS-level 1.8 V. Leave it open if unused. |
| FPD-LINK III SERIAL | |||
| DOUT0- | 26 | O | FPD-Link III Inverting Output 0
The output must be AC-coupled with a 0.1-μF capacitor for interfacing with 92x deserializers and 0.1-μF or 33-nF capacitor for 94x deserializers |
| DOUT0+ | 27 | O | FPD-Link III True Output 0
The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers and 0.1-μF or 33-nF capacitor for 94x deserializers |
| DOUT1- | 22 | O | FPD-Link III Inverting Output 1
The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers and 0.1-μF or 33-nF capacitor for 94x deserializers |
| DOUT1+ | 23 | O | FPD-Link III True Output 1
The output must be AC-coupled with a 0.1-µF capacitor for interfacing with 92x deserializers and 0.1-μF or 33-nF capacitor for 94x deserializers |
| LFT | 20 | Analog | FPD-Link III Loop Filter
Connect to a 10-nF capacitor to GND |
| CONTROL | |||
| SDA | 14 | IO, Open-Drain | I2C Data Input / Output Interface
Open-drain. Must have an external pullup to resistor to 1.8 V or 3.3 V. See I2CSEL pin. DO NOT FLOAT. Recommended pullup: 4.7 kΩ. |
| SCL | 15 | IO, Open-Drain | I2C Clock Input / Output Interface
Open-drain. Must have an external pullup resistor to 1.8 V or 3.3 V. See I2CSEL pin. DO NOT FLOAT. Recommended pullup: 4.7 kΩ. |
| I2CSEL | 6 | I, LVCMOS | I2C Voltage Level Strap Option
Tie to VDDIO with a 10-kΩ resistor for 1.8-V I2C operation. Leave floating for 3.3-V I2C operation. This pin is read as an input at power up. |
| IDx | 19 | Analog | I2C Serial Control Bus Device ID Address Select |
| MODE_SEL0 | 18 | Analog | Mode Select 0. See Table 6. |
| MODE_SEL1 | 32 | Analog | Mode Select 1. See Table 6. |
| PDB | 31 | I, LVCMOS | Power-Down Mode Input Pin |
| INTB | 13 | O, Open-Drain | Open-Drain. Remote interrupt. Active LOW.
Pull up to VDDIO with a 4.7-kΩ resistor. |
| REM_INTB | 40 | O, Open-Drain | Remote interrupt. Mirrors status of INTB_IN from the deserializer.
Note: External pull-up to 1.8 V required. Recommended pullup: 4.7 kΩ. INTB = H, Normal Operation INTB = L, Interrupt Request |
| SPI PINS (DUAL LINK MODE ONLY) | |||
| MOSI | 8 | IO, LVCMOS | SPI Master Out Slave In. Shared with D_GPIO0 |
| MISO | 10 | IO, LVCMOS | SPI Master In Slave Out. Shared with D_GPIO1 |
| SPLK | 11 | IO, LVCMOS | SPI Clock. Shared with D_GPIO2 |
| SS | 12 | IO, LVCMOS | SPI Slave Select. Shared with D_GPIO3 |
| HIGH-SPEED (HS) BIDIRECTIONAL CONTROL CHANNEL GPIO PINS (DUAL LINK MODE ONLY) | |||
| D_GPIO0 | 8 | IO, LVCMOS | HS GPIO0. Shared with MOSI |
| D_GPIO1 | 10 | IO, LVCMOS | HS GPIO1. Shared with MISO |
| D_GPIO2 | 11 | IO, LVCMOS | HS GPIO2. Shared with SPLK |
| D_GPIO3 | 12 | IO, LVCMOS | HS GPIO3. Shared with SS |
| BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS | |||
| GPIO0 | 4 | IO, LVCMOS | BCC GPIO0. Shared with SDIN |
| GPIO1 | 5 | IO, LVCMOS | BCC GPIO1. Shared with SWC |
| GPIO2 | 37 | IO, LVCMOS | BCC GPIO2. Shared with I2S_DC |
| GPIO3 | 38 | IO, LVCMOS | BCC GPIO3. Shared with I2S_DD |
| REGISTER-ONLY GPIO | |||
| GPIO5_REG | 36 | IO, LVCMOS | General-Purpose Input/Output 5
Local register control only. Shared with I2S_DB |
| GPIO6_REG | 35 | IO, LVCMOS | General-Purpose Input/Output 6
Local register control only. Shared with I2S_DA |
| GPIO7_REG | 33 | IO, LVCMOS | General-Purpose Input/Output 7
Local register control only. Shared with I2S_WC |
| GPIO8_REG | 34 | IO, LVCMOS | General-Purpose Input/Output 8
Local register control only. Shared with I2S_CLK |
| SLAVE MODE LOCAL I2S CHANNEL PINS | |||
| I2S_WC | 33 | I, LVCMOS | Slave Mode I2S Word Clock Input. Shared with GPIO7_REG |
| I2S_CLK | 34 | I, LVCMOS | Slave Mode I2S Clock Input. Shared with GPIO8_REG |
| I2S_DA | 35 | I, LVCMOS | Slave Mode I2S Data Input. Shared with GPIO6_REG |
| I2S_DB | 36 | I, LVCMOS | Slave Mode I2S Data Input. Shared with GPIO5_REG |
| I2S_DC | 37 | I, LVCMOS | Slave Mode I2S Data Input. Shared with GPIO2 |
| I2S_DD | 38 | I, LVCMOS | Slave Mode I2S Data Input. Shared with GPIO3 |
| AUXILIARY I2S CHANNEL PINS | |||
| SWC | 5 | O, LVCMOS | Master Mode I2S Word Clock Ouput. Shared with GPIO1 |
| SCLK | 6 | O, LVCMOS | Master Mode I2S Clock Ouput. Shared with I2CSEL. This pin is sampled following power-up as I2CSEL, then it will switch to SCLK operation as an output. |
| SDIN | 4 | I, LVCMOS | Master Mode I2S Data Input. Shared with GPIO0 |
| MCLK | 16 | IO, LVCMOS | Master Mode I2S System Clock Input/Output |
| POWER and GROUND | |||
| VTERM | 57 | Power | 3.3-V (±5%) Supply for DC-coupled internal termination OR
1.8-V (±5%) Supply for AC-coupled internal termination Refer to Figure 25 or Figure 26. |
| VDD18 | 24
51 64 |
Power | 1.8-V (±5%) Analog supply. Refer to Figure 25 or Figure 26. |
| VDDA11 | 9 | Power | 1.1-V (±5%) Analog supply. Refer to Figure 25 or Figure 26. |
| VDDHA11 | 52
54 58 61 |
Power | 1.1-V (±5%) TMDS supply. Refer to Figure 25 or Figure 26. |
| VDDHS11 | 21
28 |
Power | 1.1-V (±5%) supply. Refer to Figure 25 or Figure 26. |
| VDDL11 | 7
41 |
Power | 1.1-V (±5%) Digital supply. Refer to Figure 25 or Figure 26. |
| VDDP11 | 17 | Power | 1.1-V (±5%) PLL supply. Refer to Figure 25 or Figure 26. |
| VDDS11 | 25 | Power | 1.1-V (±5%) Serializer supply. Refer to Figure 25 or Figure 26. |
| VDDIO | 3
46 |
Power | 1.8-V (±5%) IO supply. Refer to Figure 25 or Figure 26. |
| GND | Thermal Pad | GND | Ground. Connect to Ground plane with at least 9 vias. |
| OTHER | |||
| RES0
RES1 |
2
29 |
— | Reserved. Tie to GND. |
| RES2 | 30 | — | Reserved. Connect with 50 Ω to GND. |
| NC0
NC1 NC2 |
47
48 53 |
— | No connect. Leave floating. Do not connect to VDD or GND. |