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ZHCSIP7B August 2018 – September 2023 DS90UB962-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RTD|64
- MPQF141C

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RTD|64
- PPTD346A

訂購信息

6.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER		TEST CONDITIONS	PIN OR FREQUENCY	MIN	TYP	MAX	UNIT
LVCMOS I/O
t_CLH	LVCMOS low-to-high transition time	V_(VDDIO) = 1.71 V to 1.89 V OR V_{(VDDIO) =} 3.0 V to 3.6 V C_L = 8 pF (lumped load) Default Registers (Figure 6-1)	GPIO[7:0]		2.5		ns
t_CHL	LVCMOS high-to-low transition time		GPIO[7:0]		2.5		ns
t_PDB	PDB reset pulse width	Power supplies applied and stable (Figure 8-14)	PDB	2			ms
FPD-LINK III RECEIVER INPUT
V_IN	Single ended input voltage	Coaxial cable attenuation = -19.2 dB @ 2.1 GHz	RIN0+, RIN0-, RIN1+, RIN1-, RIN2+, RIN2-, RIN3+, RIN3-	60			mV
V_ID	Differential input voltage	STP cable attenuation = -19.6 dB @ 2.1 GHz		115			mV
t_DDLT	Deserializer data lock time	CSI-2 Mode, paired with DS90UB935-Q1, coaxial cable attenuation = -19.2 dB @ 2.1 GHz, AEQ range +/-3			15	30	ms
		CSI-2 Mode, paired with DS90UB935-Q1, coaxial cable attenuation = -19.2 dB @ 2.1 GHz, AEQ default range			400		ms
		Raw Mode, paired with DS90UB933-Q1, coaxial cable attenuation = -14 dB @ 1.4 GHz, AEQ range +/-3			15	30	ms
		Raw Mode, paired with DS90UB933-Q1, coaxial cable attenuation = -14 dB @ 1.4 GHz, AEQ default range			400		ms
t_IJIT	Input jitter	CSI-2 Mode, paired with DS90UB935-Q1, coaxial cable attenuation = -19.2 dB @ 2.1 GHz, Jitter frequency > FPD3_PCLK⁽¹⁾ / 15 See Section 7.4.6				0.4	UI
t_IJIT	Input jitter	CSI-2 Mode, paired with DS90UB935-Q1, STP cable attenuation = -19.6 dB @ 2.1 GHz, Jitter frequency > FPD3_PCLK⁽¹⁾ / 15 See Section 7.4.6				0.4	UI
FPD-LINK III BACK CHANNEL DRIVER
E_W-BC	Back channel output eye width	Coaxial or STP configuration, f_BC = 52 Mbps	RIN0+, RIN0-, RIN1+, RIN1-, RIN2+, RIN2-, RIN3+, RIN3-	0.7	0.8		UI_BC
E_H-BC	Back channel output eye height	Coaxial configuration, f_BC = 52 Mbps		130	160		mV
E_H-BC	Back channel output eye height	STP configuration, f_BC = 52 Mbps		260	320		mV
f_BC	Back channel data	CSI-2 synchronous mode	RIN0+, RIN0-, RIN1+, RIN1-, RIN2+, RIN2-, RIN3+, RIN3-		2x REFCLK		Mbps
		CSI-2 synchronous mode, no REFCLK		46		56	Mbps
		CSI-2 non-synchronous mode			2x REFCLK/5		Mbps
		Raw mode			REFCLK/10		Mbps

(1) FPD3_PCLK frequency is a function of the PCLK, CLK_IN or REFCLK frequency and dependent on the serializer operating MODE:
CSI-2 syncronous mode: FPD3_PCLK = 4 x REFCLK
CSI-2 non-syncronous mode: FPD3_PCLK = 2 x CLK_IN
RAW 10-bit mode: FPD3_PCLK = PCLK / 2
RAW 12-bit HF mode: FPD3_PCLK = 2 x PCLK / 3
RAW 12-bit LF mode: FPD3_PCLK = PCLK