4 Revision History

Changes from Revision A (December 2020) to Revision B (September 2023)

• 通篇更正了拼寫錯誤和格式小問題Go
• 從器件特性列表中刪除了“端口復制模式”Go
• Fixed spelling errors and minor format issues throughout the document Go
• Updated I2C pull-up resistor recommendationsGo
• Updated Legend for Pin Functions TableGo
• Removed the t_CLK-MISS specification from the CSI-2 Timing Specifications tableGo
• Updated Timing Diagrams section figure titles to align with the figuresGo
• Removed obstructions in CSI-2 General Frame Format figure to make text clearerGo
• Updated the title of the section with timing figures to Timing DiagramsGo
• Clarified the clock speed and the configuration settings of non-synchronous clock modeGo
• Added information about YUV supportGo
• Added clarification that MODE pin option 0 straps the device to CSI-2 Non-Synchronous back channel and MODE pin option 4 straps the device to CSI-2 Synchronous back channelGo
• Changed I2C terminology to "Controller" and "Target"Go
• Added a channel requirements section to the datasheetGo
• Fixed spelling errors throughout the documentGo
• Fixed spelling errors throughout the documentGo
• Added information about YUV supportGo
• Removed mention of older siliconGo
• Removed CSI-2 Transmitter Frequency script example for unsupported CSI-2 portGo
• Added cross-links in the CSI-2 Output Bandwidth section to relevant figures in the Timing Diagrams sectionGo
• Fixed spelling errors throughout the documentGo
• Added a sentence to clarify that V_I2C must match the voltage applied to VDDIOGo
• Reworded the Serial Control Bus section to reference V_I2C instead of VDDIOGo
• Added register addresses for the RX Port ID registersGo
• Removed information suggesting that the Rx Port intended for messaging must always be selected with Register 0x4C when communicating with a remote target deviceGo
• Corrected the total number of TargetID and Target Alias pairs of registers for the deviceGo
• Clarified that the write enable bit in register 0x4C needs to be set before configuring remote target addressesGo
• Added additional information about how to configure a broadcast write to remote devicesGo
• Removed unnecessary register writes in the Code Example for Broadcast WriteGo
• Updated the I2C Controller Proxy descriptionGo
• Fixed register address errors in the Typical I2C Timing Register Settings tableGo
• Removed details about the internal reference clockGo
• Corrected typo that mentions two CSI-2 Transmit ports in the Interrupt Support sectionGo
• Replaced CABLE_FAULT with NO_FPD3_CLK in the interrupt readback example script to match the register bit nameGo
• Clarified instructions for how to configure Pattern Generation on the CSI-2 PortGo
• Removed all RESERVED registers from the datasheetGo
• Updated description of registers 0x10-0x17 to remove mention of unsupported CSI-2 TX PortGo
• RESERVED register bits 0x20[3:0] that have no customer use caseGo
• RESERVED register bit 0x32[4] that has no customer use caseGo
• Made register bits 0x34[5:4] public and updated the description of register bit 0x34[1]Go
• Corrected a bit description typo for bit 4 of register 0x4AGo
• Updated the description of register bit 0x4E[1] to clarify functionalityGo
• Updated the description sections of registers 0x51-0x54Go
• Fixed typos in the description for registers 0x90-0x97Go
• Removed RESERVED indirect register pages in the description of register bits 0xB0[5:2]Go
• Made register 0xB6 publicGo
• Updated the bit description of 0xB9[3:0]Go
• Updated the name of Indirect Register Page 0 to PATGEN_AND_CSI-2Go
• Updated the PoC descriptionGo
• Updated all typical connection diagrams to include a reference to App Note SLVA689Go
• Added clarification for the recommended ferrite bead characteristics on the power supply railsGo
• Removed optional 10 kΩ pulldown resistor on Pin 4 in the Typical Connection DiagramGo
• Added clarification for the NC pin connections in the Typical Connection DiagramGo
• Updated MIPI CSI-2 D-PHY layout recommendationsGo