ZHCSIP7B August 2018 – September 2023 DS90UB962-Q1
PRODUCTION DATA
The DS90UB962-Q1 implements logic to detect skew between video signaling from attached sensors. For each input port, the DS90UB962-Q1 provides the ability to capture a time-stamp for both a start-of-frame and start-of-line event. Comparison of timestamps can provide information on the relative skew between the ports. Start-of-frame timestamps are generated at the active edge of the Vertical Sync signal in Raw mode. Start-of-line timestamps are generated at the start of reception of the Nth line of video data after the Start of Frame for either mode of operation. The function does not use the Line Start (LS) packet or Horizontal Sync controls to determine the start of lines.
The skew detection can run in either a FrameSync mode or free-run mode.
Skew detection can be individually enabled for each RX port.
For start-of-line timestamps, a line number must be programmed. The same line number is used for all 4 channels. Prior to reading timestamps, the TS_FREEZE bit for each port that will be read should be set. This will prevent overwrite of the timestamps by the detection circuit until all timestamps have been read. The freeze condition will be released automatically once all frozen timestamps have been read. The freeze bits can also be cleared if it does not read all the timestamp values.
The TS_STATUS register includes the following:
The Timestamp Ready flag will be cleared when the TS_FREEZE bit is cleared.