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ZHCSIG1D August 2016 – September 2023 DS90UB960-Q1

PRODUCTION DATA

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6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER		TEST CONDITIONS		PIN OR FREQUENCY	MIN	TYP	MAX	UNIT
POWER CONSUMPTION
P_T	Total power consumption in operation mode	CSI-2 TX = 2 x (4 data lanes + 1 CLK lane) CSI-2 TX line rate = 1.664 Gbps 4 × FPD-Link III RX inputs FPD-Link III line rate = 4.16 Gbps CSI-2 mode, Non-replicate mode Default registers		VDD18, VDD11, VDDIO		800	999	mW
SUPPLY CURRENT
I_DDT1	Deserializer supply current (includes load current)	CSI-2 TX = 4 data lanes + 1 CLK lane CSI-2 TX line rate = 1.664 Gbps 4 × FPD-Link III RX inputs FPD-Link III line rate = 4.16 Gbps CSI-2 mode, Non-replicate mode Default registers		VDD11		165	310	mA
				VDD18		295	340
				VDDIO		2	3
		CSI-2 TX = 4 data lanes + 1 CLK lane CSI-2 TX line rate = 832 Mbps 4 × FPD-Link III RX inputs FPD-Link III line rate = 4.16 Gbps CSI-2 mode, Non-replicate mode Default registers		VDD11		150	290	mA
				VDD18		295	340
				VDDIO		2	3
I_DDT2	Deserializer supply current (includes load current)	CSI-2 TX = 2 x (4 data lanes + 1 CLK lane) CSI-2 TX line rate = 1.664 Gbps 4 × FPD-Link III RX inputs FPD-Link III line rate = 4.16 Gbps CSI-2 mode, Replicate mode Default registers		VDD11		174	360	mA
				VDD18		312	370
				VDDIO		2	3
		CSI-2 TX = 2 x (4 data lanes + 1 CLK lane) CSI-2 TX line rate = 832 Mbps 4 × FPD-Link III RX inputs FPD-Link III line rate = 4.16 Gbps CSI-2 mode, Replicate mode Default registers		VDD11		127	305	mA
				VDD18		369	415
				VDDIO		2	3
I_DDT3	Deserializer supply current (includes load current)	CSI-2 TX = 4 data lanes + 1 CLK lane CSI-2 TX line rate = 1.664 Gbps 4 × FPD-Link III RX inputs FPD-Link III line rate = 1.867 Gbps RAW12 HF mode, Non-replicate mode Default registers		VDD11		122	300	mA
				VDD18		263	305
				VDDIO		2	3
		CSI-2 TX = 2 x (4 data lanes + 1 CLK lane) CSI-2 TX line rate = 832 Mbps 4 × FPD-Link III RX inputs FPD-Link III line rate = 1.867 Gbps RAW12 HF mode, Replicate mode Default registers		VDD11		120	330	mA
				VDD18		315	365
				VDDIO		2	3
I_DDZ	Deserializer shutdown current	PDB = LOW		VDD11			160	mA
				VDD18			4
				VDDIO			3
1.8-V LVCMOS I/O
V_OH	High level output voltage	I_OH = –2 mA, V_(VDDIO) = 1.71 to 1.89 V		GPIO[7:0]	V_(VDDIO) – 0.45		V_(VDDIO)	V
V_OL	Low level output voltage	I_OL = 2 mA, V_(VDDIO) = 1.71 to 1.89 V		GPIO[7:0], INTB	GND		0.45	V
V_IH	High level input voltage	V_(VDDIO) = 1.71 to 1.89 V		GPIO[7:0], PDB, REFCLK	0.65 × V_(VDDIO)		V_(VDDIO)	V
V_IL	Low level input voltage	V_(VDDIO) = 1.71 to 1.89 V		GPIO[7:0], PDB, REFCLK	GND		0.35 × V_(VDDIO)	V
I_IH	Input high current	V_IN = V_(VDDIO) = 1.71 to 1.89 V, internal pulldown enabled		GPIO[7:0], PDB	45		115	μA
I_IH	Input high current	V_IN = V_(VDDIO) = 1.71 to 1.89 V, internal pulldown disabled		GPIO[7:0], REFCLK			20	μA
I_IL	Input low current	V_IN = 0 V		GPIO[7:0], PDB, REFCLK	–20		3.5	μA
I_IN-STRAP	Strap pin input current	V_IN = 0 V to V_(VDD18)		MODE, IDX	–1		1	μA
I_OS	Output short circuit current	V_OUT = 0 V		GPIO[7:0]		–40		mA
I_OZ	TRI-STATE output current	V_OUT = 0 V or V_(VDDIO) , PDB = LOW		GPIO[7:0]	–20		20	μA
3.3-V LVCMOS I/O
V_OH	High level output voltage	I_OH = –4 mA, V_(VDDIO) = 3.0 to 3.6 V		GPIO[7:0]	2.4		V_(VDDIO)	V
V_OL	Low level output voltage	I_OL = 4 mA, V_(VDDIO) = 3.0 to 3.6 V		GPIO[7:0], INTB	GND		0.4	V
V_IH	Highlevel input voltage	V_(VDDIO) = 3.0 to 3.6 V		GPIO[7:0], REFCLK	2		V_(VDDIO)	V
V_IH	Highlevel input voltage	V_(VDDIO) = 3.0 to 3.6 V		PDB	1.17		V_(VDDIO)	V
V_IL	Low level input voltage	V_(VDDIO) = 3.0 to 3.6 V		GPIO[7:0], REFCLK	GND		0.8	V
V_IL	Low level input voltage	V_(VDDIO) = 3.0 to 3.6 V		PDB	GND		0.63	V
I_IH	Input high current	V_IN = V_(VDDIO) = 3.0 to 3.6 V, internal pulldown enabled		GPIO[7:0], PDB	85		215	μA
I_IH	Input high current	V_IN = V_(VDDIO) = 3.0 to 3.6 V, internal pulldown disabled		GPIO[7:0], REFCLK			30	μA
I_IL	Input low current	V_IN = V_(VDDIO) = 0 V		GPIO[7:0], PDB, REFCLK	–20		3.5	μA
I_OS	Output short circuit current	V_OUT = 0 V		GPIO[7:0]		–65		mA
I_OZ	TRI-STATE output current	V_OUT = 0 V or V_(VDDIO) , PDB = LOW		GPIO[7:0]	–20		30	μA
I²C SERIAL CONTROL BUS
V_IH	Input high level			I2C_SDA, I2C_SCL I2C_SDA2, I2C_SCL2	0.7 × V_(I2C)		V_(I2C)	V
V_IL	Input low level				GND		0.3 × V_(I2C)	V
V_HYS	Input hysteresis					50		mV
V_OL1	Output low level	V_(I2C) = 3.0 to 3.6 V, I_OL = 3 mA	Standard-mode Fast-mode		0		0.4	V
V_OL1	Output low level	V_(I2C) = 3.0 to 3.6 V, I_OL = 20 mA	Fast-mode Plus		0		0.4	V
V_OL2	Output low level	V_(I2C) = 1.71 to 1.89 V, I_OL = 2 mA	Fast-mode Fast-mode Plus		0		0.2 × V_(I2C)	V
I_IN	Input current	V_IN = 0 V or V_(I2C)			–10		10	μA
C_IN	Input capacitance					5		pF
FPD-LINK III RECEIVER INPUT
V_CM	Common mode voltage			RIN0+, RIN0-, RIN1+, RIN1-, RIN2+, RIN2-, RIN3+, RIN3-		1.2		V
R_T	Internal termination resistance	Single-ended RIN+ or RIN-			40	50	60	?
R_T	Internal termination resistance	Differential across RIN+ and RIN-			80	100	120	?
FPD-LINK III BACK CHANNEL DRIVER OUTPUT
V_OUT-BC	Back channel single-ended output voltage	R_L = 50 Ω Coaxial configuration Forward channel disabled		RIN0+, RIN1+ RIN2+, RIN3+	190	220	260	mV
V_OD-BC	Back channel differential output voltage V_(RIN+) - V_(RIN-)	R_L = 100 Ω STP configuration Forward channel disabled		RIN0+, RIN0-, RIN1+, RIN1-, RIN2+, RIN2-, RIN3+, RIN3-	380	440	520	mV
HSTX DRIVER
V_CMTX	HS transmit static common-mode voltage			CSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI0_CLKP, CSI0_CLKN, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N, CSI1_CLKP, CSI1_CLKN	150	200	250	mV
\|ΔV_CMTX(1,0)\|	V_CMTX mismatch when output is 1 or 0						5	mV_P-P
\|V_OD\|	HS transmit differential voltage				140	200	270	mV
\|ΔV_OD\|	V_OD mismatch when output is 1 or 0						14	mV
V_OHHS	HS output high voltage						360	mV
Z_OS	Single-ended output impedance				40	50	62.5	Ω
ΔZ_OS	Mismatch in single-ended output impedance						10	%
LPTX DRIVER
V_OH	High level output voltage	CSI-2 TX line rate ≤ 1.5 Gbps		CSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI0_CLKP, CSI0_CLKN, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N, CSI1_CLKP, CSI1_CLKN	1.1	1.2	1.3	V
V_OH	High level output voltage	CSI-2 TX line rate > 1.5 Gbps			0.95		1.3	V
V_OL	Low level output voltage				–50		50	mV
Z_OLP	Output impedance				110			Ω

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機械數據 (封裝 | 引腳)

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6.5 DC Electrical Characteristics