ZHCSGT3C August 2017 – January 2023 DS90UB954-Q1
PRODUCTION DATA
RX port specific register. The FPD-Link III Port Select register 0x4C configures which unique RX port registers can be accessed by I2C read and write commands.
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7:5 | ADAPTIVE_EQ _RELOCK_TIME | R/W | 0x4 | Time to wait for lock before incrementing the EQ to next setting 000 : 164 μs 001 : 328 μs 010 : 655 μs 011 : 1.31 ms 100 : 2.62 ms 101 : 5.24 ms 110 : 10.5 ms 111 : 21.0 ms |
| 4 | AEQ_1ST_LOCK _MODE | R/W | 0x1 | AEQ First Lock Mode. This register bit controls the Adaptive Equalizer algorithm operation at initial Receiver Lock. 0 : Initial AEQ lock may occur at any value 1 : Initial Receiver lock will restart AEQ at 0, providing a more deterministic initial AEQ value |
| 3 | AEQ_RESTART | (R/W)/SC | 0x0 | Set high to restart AEQ adaptation from initial value. This bit is self clearing. Adaption is restarted. |
| 2 | SET_AEQ_FLOOR | R/W | 0x1 | AEQ adaptation starts from a pre-set floor value rather than from zero - good in long cable situations |
| 1:0 | RESERVED | R | 0x0 | Reserved |