ZHCSGT3C August 2017 – January 2023 DS90UB954-Q1
PRODUCTION DATA
Since the BCC buffers each I2C data byte and regenerates the I2C protocol on the remote side of the link, the overall I2C throughput will be reduced. The reduction is dependent on the operating frequencies of the local and remote interfaces. The local I2C rate is based on the host controller clock rate, while the remote rate depends on the settings for the proxy I2C controller (SCL frequency).
For purposes of understanding the effects of the BCC on data throughput from a host controller to a remote I2C controller, the approximate bit rate including latency timings across the control channel can be calculated by the following:
9 bits / ((Host_bit * 9) + (Remote_bit * 9) + FCdelay + BCCdelay)
Example of DS90UB953/954 chipset:
For the 100 kbit/s (100 kHz) :
Host_bit = 10us (100 kHz)
Remote_bit = 13.5us (default 74 kHz)
FCdelay = 225ns (typical value)
BCCdelay = 1.5us (typical value for 50 Mbps back channel rate)
Effective rate = 9bits / (90us + 121us + 0.225us + 1.5us) = 42.3 kbit/s
| Host I2C rate | Remote I2C rate | Net bit rate |
|---|---|---|
| 100 kbit/s | 74 kbit/s (default settings) | 42.3 kbit/s |
| 400 kbit/s | 100 kbit/s | 78.8 kbit/s |
| 1 Mbit/s | 100 kbit/s | 89.4 kbit/s |
| 1 Mbit/s | 400 kbit/s | 270.88 kbit/s |
| 1 Mbit/s | 1 Mbit/s | 456.27 kbit/s |
Since the I2C protocol includes overhead for sending address information as well as START and STOP bits, the actual data throughput depends on the size and type of transactions used. Use of large bursts to read and write data will result in higher data transfer rates.