99精品国产在热久久婷婷,妇女性内射冈站hdwww000,中文无码一区二区三区不卡av

ZHCSGT3C August 2017 – January 2023 DS90UB954-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RGZ|48
- MPQF123F

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RGZ|48
- QFND014T

訂購信息

7.4.14 Line Valid and Frame Valid Indicators

The FrameValid (FV) and LineValid (LV) indications from the Receive Port indicate approximate frame and line boundaries at the FPD-Link III Receiver input. These signals may not be accurate if the receiver is in CSI-2 input mode and multiple video streams are present at the Receive Port input. A common example of this scenario would be multiple Virtual Channel IDs received on a single port.

When the receiver is in one of the Raw modes the LV and FV provides controls for the video framing. The FV is equivalent to a Vertical Sync (VSYNC) while the LineValid is equivalent to a Horizontal Sync (HSYNC) input to the DS90UB933A-Q1 and DS90UB913A-Q1 device (see GUID-DADE79CE-A2B9-46FA-81B2-84BAB7298C4D.html#GUID-DADE79CE-A2B9-46FA-81B2-84BAB7298C4D).

The DS90UB954-Q1 allows setting the polarity of these signals by register programming. The FV and LV polarity are controlled on a per-port basis and can be independently set in the PORT_CONFIG2 register 0x7C.

To prevent false detection of FrameValid, FV must be asserted for a minimum number of clocks prior to first video line to be considered valid. The minimum FrameValid time is programmable in the FV_MIN_TIME register 0xBC. Because the measurement is in FPD-Link III clocks, the minimum FrameValid setup to LineValid timing at the Serializer will vary based on the RAW input operating mode.

A minimum FV to LV timing is required when processing RAW video frames at the serializer input. If the FV to LV minimum setup is not met (by default), the first video line is discarded. Optionally, a register control (PORT_CONFIG:DISCARD_1ST_ON_ERR) forwards the first video line missing some number of pixels at the start of the line.

Figure 7-7 Minimum FV to LV

Table 7-11 Minimum FV to LV Setup Requirement (in RAW Mode Serializer FPD-Link III PCLKs)

MODE	FV_MIN_TIME CONVERSION FACTOR	ABSOLUTE MIN (FV_MIN_TIME = 0)	DEFAULT (FV_MIN_TIME = 128)
RAW12 HF	1.5	3	195
RAW10	2	5	261

For other settings of FV_MIN_TIME, the required FV to LV setup in Serializer PCLKs can be determined by:

Absolute Min + (FV_MIN_TIME × Conversion factor)