ZHCSGT3C August 2017 – January 2023 DS90UB954-Q1
PRODUCTION DATA
RX port specific register. The FPD-Link III Port Select register 0x4C configures which unique RX port registers can be accessed by I2C read and write commands.
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7 | PASS_DISCARD_EN | R/W | 0x0 | Pass Discard Enable Discard packets if PASS is not indicated. 0 : Ignore PASS for forwarding packets 1 : Discard packets when PASS is not true |
| 6 | RESERVED | R/W | 0x0 | Reserved |
| 5 | PASS_LINE_CNT | R/W | 0x0 | Pass Line Count Control This register controls whether the device will include line count in qualification of the Pass indication: 0 : Don't check line count 1 : Check line count When checking line count, Pass is deasserted upon detection of a change in the number of video lines per frame. Pass will not be reasserted until the PASS_THRESHOLD setting is met. |
| 4 | PASS_LINE_SIZE | R/W | 0x0 | Pass Line Size Control This register controls whether the device will include line size in qualification of the Pass indication: 0 : Don't check line size 1 : Check line size When checking line size, Pass is deasserted upon detection of a change in video line size. Pass will not be reasserted until the PASS_THRESHOLD setting is met. |
| 3 | PASS_PARITY_ERR | R/W | x00 | Parity Error Mode If this bit is set to 0, the port Pass indication is deasserted for every parity error detected on the FPD-Link III Receive interface. If this bit is set to a 1, the port Pass indication is cleared on a parity error and remain clear until the PASS_THRESHOLD is met. When PASS_PARITY_ERR is set to 1, TI also recommends setting PASS_THRESHOLD to 2 or higher to ensure at least one good frame occurs following a parity error |
| 2 | PASS_WDOG_DIS | R/W | 0x0 | RX Port Pass Watchdog disable When enabled, if the FPD Receiver does not detect a valid frame end condition within two video frame periods, the Pass indication is deasserted. The watchdog timer will not have any effect if the PASS_THRESHOLD is set to 0. 0 : Enable watchdog timer for RX Pass 1 : Disable watchdog timer for RX Pass |
| 1:0 | PASS_THRESHOLD | R/W | 0x0 | Pass Threshold Register This register controls the number of valid frames before asserting the port Pass indication. If set to 0, PASS is asserted after Receiver Lock detect. If non-zero, PASS is asserted following reception of the programmed number of valid frames. |